1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 #define CONFIG_SYS_THUMB_BUILD 13 14 /* 15 * High level configuration 16 */ 17 #define CONFIG_DISPLAY_CPUINFO 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 #define CONFIG_ARCH_MISC_INIT 20 #define CONFIG_ARCH_EARLY_INIT_R 21 #define CONFIG_SYS_NO_FLASH 22 #define CONFIG_CLOCKS 23 24 #define CONFIG_CRC32_VERIFY 25 26 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* add target to build it automatically upon "make" */ 31 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 32 33 /* 34 * Memory configurations 35 */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define PHYS_SDRAM_1 0x0 38 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 39 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 40 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 41 42 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 43 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 44 #define CONFIG_SYS_INIT_SP_OFFSET \ 45 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 48 49 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 51 #define CONFIG_SYS_TEXT_BASE 0x08000040 52 #else 53 #define CONFIG_SYS_TEXT_BASE 0x01000040 54 #endif 55 56 /* 57 * U-Boot general configurations 58 */ 59 #define CONFIG_SYS_LONGHELP 60 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 61 #define CONFIG_SYS_PBSIZE \ 62 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 63 /* Print buffer size */ 64 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 65 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 66 /* Boot argument buffer size */ 67 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 68 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 69 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 70 71 #ifndef CONFIG_SYS_HOSTNAME 72 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 73 #endif 74 75 /* 76 * Cache 77 */ 78 #define CONFIG_SYS_CACHELINE_SIZE 32 79 #define CONFIG_SYS_L2_PL310 80 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 81 82 /* 83 * SDRAM controller 84 */ 85 #define CONFIG_ALTERA_SDRAM 86 87 /* 88 * EPCS/EPCQx1 Serial Flash Controller 89 */ 90 #ifdef CONFIG_ALTERA_SPI 91 #define CONFIG_SF_DEFAULT_SPEED 30000000 92 /* 93 * The base address is configurable in QSys, each board must specify the 94 * base address based on it's particular FPGA configuration. Please note 95 * that the address here is incremented by 0x400 from the Base address 96 * selected in QSys, since the SPI registers are at offset +0x400. 97 * #define CONFIG_SYS_SPI_BASE 0xff240400 98 */ 99 #endif 100 101 /* 102 * Ethernet on SoC (EMAC) 103 */ 104 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 105 #define CONFIG_DW_ALTDESCRIPTOR 106 #define CONFIG_MII 107 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 108 #define CONFIG_PHY_GIGE 109 #endif 110 111 /* 112 * FPGA Driver 113 */ 114 #ifdef CONFIG_CMD_FPGA 115 #define CONFIG_FPGA 116 #define CONFIG_FPGA_ALTERA 117 #define CONFIG_FPGA_SOCFPGA 118 #define CONFIG_FPGA_COUNT 1 119 #endif 120 121 /* 122 * L4 OSC1 Timer 0 123 */ 124 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 125 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 126 #define CONFIG_SYS_TIMER_COUNTS_DOWN 127 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 128 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 129 #define CONFIG_SYS_TIMER_RATE 2400000 130 #else 131 #define CONFIG_SYS_TIMER_RATE 25000000 132 #endif 133 134 /* 135 * L4 Watchdog 136 */ 137 #ifdef CONFIG_HW_WATCHDOG 138 #define CONFIG_DESIGNWARE_WATCHDOG 139 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 140 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 141 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 142 #endif 143 144 /* 145 * MMC Driver 146 */ 147 #ifdef CONFIG_CMD_MMC 148 #define CONFIG_MMC 149 #define CONFIG_BOUNCE_BUFFER 150 #define CONFIG_GENERIC_MMC 151 #define CONFIG_DWMMC 152 #define CONFIG_SOCFPGA_DWMMC 153 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 154 /* FIXME */ 155 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 156 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 157 #endif 158 159 /* 160 * NAND Support 161 */ 162 #ifdef CONFIG_NAND_DENALI 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 164 #define CONFIG_SYS_NAND_MAX_CHIPS 1 165 #define CONFIG_SYS_NAND_ONFI_DETECTION 166 #define CONFIG_NAND_DENALI_ECC_SIZE 512 167 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 168 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 169 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 170 #endif 171 172 /* 173 * I2C support 174 */ 175 #define CONFIG_SYS_I2C 176 #define CONFIG_SYS_I2C_BUS_MAX 4 177 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 178 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 179 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 180 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 181 /* Using standard mode which the speed up to 100Kb/s */ 182 #define CONFIG_SYS_I2C_SPEED 100000 183 #define CONFIG_SYS_I2C_SPEED1 100000 184 #define CONFIG_SYS_I2C_SPEED2 100000 185 #define CONFIG_SYS_I2C_SPEED3 100000 186 /* Address of device when used as slave */ 187 #define CONFIG_SYS_I2C_SLAVE 0x02 188 #define CONFIG_SYS_I2C_SLAVE1 0x02 189 #define CONFIG_SYS_I2C_SLAVE2 0x02 190 #define CONFIG_SYS_I2C_SLAVE3 0x02 191 #ifndef __ASSEMBLY__ 192 /* Clock supplied to I2C controller in unit of MHz */ 193 unsigned int cm_get_l4_sp_clk_hz(void); 194 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 195 #endif 196 197 /* 198 * QSPI support 199 */ 200 /* Enable multiple SPI NOR flash manufacturers */ 201 #ifndef CONFIG_SPL_BUILD 202 #define CONFIG_SPI_FLASH_MTD 203 #define CONFIG_CMD_MTDPARTS 204 #define CONFIG_MTD_DEVICE 205 #define CONFIG_MTD_PARTITIONS 206 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 207 #endif 208 /* QSPI reference clock */ 209 #ifndef __ASSEMBLY__ 210 unsigned int cm_get_qspi_controller_clk_hz(void); 211 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 212 #endif 213 #define CONFIG_CQSPI_DECODER 0 214 215 /* 216 * Designware SPI support 217 */ 218 219 /* 220 * Serial Driver 221 */ 222 #define CONFIG_SYS_NS16550_SERIAL 223 #define CONFIG_SYS_NS16550_REG_SIZE -4 224 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 225 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 226 #define CONFIG_SYS_NS16550_CLK 1000000 227 #else 228 #define CONFIG_SYS_NS16550_CLK 100000000 229 #endif 230 #define CONFIG_CONS_INDEX 1 231 #define CONFIG_BAUDRATE 115200 232 233 /* 234 * USB 235 */ 236 #ifdef CONFIG_CMD_USB 237 #define CONFIG_USB_DWC2 238 #define CONFIG_USB_STORAGE 239 #endif 240 241 /* 242 * USB Gadget (DFU, UMS) 243 */ 244 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 245 #define CONFIG_USB_FUNCTION_MASS_STORAGE 246 247 #define CONFIG_USB_FUNCTION_DFU 248 #ifdef CONFIG_DM_MMC 249 #define CONFIG_DFU_MMC 250 #endif 251 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 252 #define DFU_DEFAULT_POLL_TIMEOUT 300 253 254 /* USB IDs */ 255 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 256 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 257 #endif 258 259 /* 260 * U-Boot environment 261 */ 262 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 263 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 264 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 265 #if !defined(CONFIG_ENV_SIZE) 266 #define CONFIG_ENV_SIZE 4096 267 #endif 268 269 /* Environment for SDMMC boot */ 270 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 271 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 272 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 273 #endif 274 275 /* Environment for QSPI boot */ 276 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 277 #define CONFIG_ENV_OFFSET 0x00100000 278 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 279 #endif 280 281 /* 282 * mtd partitioning for serial NOR flash 283 * 284 * device nor0 <ff705000.spi.0>, # parts = 6 285 * #: name size offset mask_flags 286 * 0: u-boot 0x00100000 0x00000000 0 287 * 1: env1 0x00040000 0x00100000 0 288 * 2: env2 0x00040000 0x00140000 0 289 * 3: UBI 0x03e80000 0x00180000 0 290 * 4: boot 0x00e80000 0x00180000 0 291 * 5: rootfs 0x01000000 0x01000000 0 292 * 293 */ 294 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 295 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 296 "1m(u-boot)," \ 297 "256k(env1)," \ 298 "256k(env2)," \ 299 "14848k(boot)," \ 300 "16m(rootfs)," \ 301 "-@1536k(UBI)\0" 302 #endif 303 304 /* UBI and UBIFS support */ 305 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 306 #define CONFIG_CMD_UBI 307 #define CONFIG_CMD_UBIFS 308 #define CONFIG_RBTREE 309 #define CONFIG_LZO 310 #endif 311 312 /* 313 * SPL 314 * 315 * SRAM Memory layout: 316 * 317 * 0xFFFF_0000 ...... Start of SRAM 318 * 0xFFFF_xxxx ...... Top of stack (grows down) 319 * 0xFFFF_yyyy ...... Malloc area 320 * 0xFFFF_zzzz ...... Global Data 321 * 0xFFFF_FF00 ...... End of SRAM 322 */ 323 #define CONFIG_SPL_FRAMEWORK 324 #define CONFIG_SPL_RAM_DEVICE 325 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 326 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 327 #ifdef CONFIG_SPL_BUILD 328 #define CONFIG_SYS_MALLOC_SIMPLE 329 #endif 330 331 #define CONFIG_SPL_LIBCOMMON_SUPPORT 332 #define CONFIG_SPL_LIBGENERIC_SUPPORT 333 #define CONFIG_SPL_WATCHDOG_SUPPORT 334 #define CONFIG_SPL_SERIAL_SUPPORT 335 #ifdef CONFIG_DM_MMC 336 #define CONFIG_SPL_MMC_SUPPORT 337 #endif 338 #ifdef CONFIG_DM_SPI 339 #define CONFIG_SPL_SPI_SUPPORT 340 #endif 341 #ifdef CONFIG_SPL_NAND_DENALI 342 #define CONFIG_SPL_NAND_SUPPORT 343 #endif 344 345 /* SPL SDMMC boot support */ 346 #ifdef CONFIG_SPL_MMC_SUPPORT 347 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 348 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 349 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 350 #define CONFIG_SPL_LIBDISK_SUPPORT 351 #else 352 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 353 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 354 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 355 #endif 356 #endif 357 358 /* SPL QSPI boot support */ 359 #ifdef CONFIG_SPL_SPI_SUPPORT 360 #define CONFIG_SPL_SPI_FLASH_SUPPORT 361 #define CONFIG_SPL_SPI_LOAD 362 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 363 #endif 364 365 /* SPL NAND boot support */ 366 #ifdef CONFIG_SPL_NAND_SUPPORT 367 #define CONFIG_SYS_NAND_USE_FLASH_BBT 368 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 369 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 370 #endif 371 372 /* 373 * Stack setup 374 */ 375 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 376 377 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 378