1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* 18 * Memory configurations 19 */ 20 #define PHYS_SDRAM_1 0x0 21 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 22 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 23 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 24 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 25 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 26 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 27 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 29 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 30 #endif 31 32 /* 33 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 34 * SRAM as bootcounter storage. Make sure to not put the stack directly 35 * at this address to not overwrite the bootcounter by checking, if the 36 * bootcounter address is located in the internal SRAM. 37 */ 38 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 39 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 40 CONFIG_SYS_INIT_RAM_SIZE))) 41 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR 42 #else 43 #define CONFIG_SYS_INIT_SP_ADDR \ 44 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 45 #endif 46 47 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 48 49 /* 50 * U-Boot general configurations 51 */ 52 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 53 /* Print buffer size */ 54 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 55 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 56 /* Boot argument buffer size */ 57 58 #ifndef CONFIG_SYS_HOSTNAME 59 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 60 #endif 61 62 /* 63 * Cache 64 */ 65 #define CONFIG_SYS_L2_PL310 66 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 67 68 /* 69 * EPCS/EPCQx1 Serial Flash Controller 70 */ 71 #ifdef CONFIG_ALTERA_SPI 72 #define CONFIG_SF_DEFAULT_SPEED 30000000 73 /* 74 * The base address is configurable in QSys, each board must specify the 75 * base address based on it's particular FPGA configuration. Please note 76 * that the address here is incremented by 0x400 from the Base address 77 * selected in QSys, since the SPI registers are at offset +0x400. 78 * #define CONFIG_SYS_SPI_BASE 0xff240400 79 */ 80 #endif 81 82 /* 83 * Ethernet on SoC (EMAC) 84 */ 85 #ifdef CONFIG_CMD_NET 86 #define CONFIG_DW_ALTDESCRIPTOR 87 #endif 88 89 /* 90 * FPGA Driver 91 */ 92 #ifdef CONFIG_CMD_FPGA 93 #define CONFIG_FPGA_COUNT 1 94 #endif 95 96 /* 97 * L4 OSC1 Timer 0 98 */ 99 #ifndef CONFIG_TIMER 100 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 101 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 102 #define CONFIG_SYS_TIMER_COUNTS_DOWN 103 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 104 #define CONFIG_SYS_TIMER_RATE 25000000 105 #endif 106 107 /* 108 * L4 Watchdog 109 */ 110 #ifdef CONFIG_HW_WATCHDOG 111 #define CONFIG_DESIGNWARE_WATCHDOG 112 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 113 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 114 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 115 #endif 116 117 /* 118 * MMC Driver 119 */ 120 #ifdef CONFIG_CMD_MMC 121 /* FIXME */ 122 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 123 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 124 #endif 125 126 /* 127 * NAND Support 128 */ 129 #ifdef CONFIG_NAND_DENALI 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 131 #define CONFIG_SYS_NAND_ONFI_DETECTION 132 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 133 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 134 #endif 135 136 /* 137 * I2C support 138 */ 139 #ifndef CONFIG_DM_I2C 140 #define CONFIG_SYS_I2C 141 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 142 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 143 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 144 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 145 /* Using standard mode which the speed up to 100Kb/s */ 146 #define CONFIG_SYS_I2C_SPEED 100000 147 #define CONFIG_SYS_I2C_SPEED1 100000 148 #define CONFIG_SYS_I2C_SPEED2 100000 149 #define CONFIG_SYS_I2C_SPEED3 100000 150 /* Address of device when used as slave */ 151 #define CONFIG_SYS_I2C_SLAVE 0x02 152 #define CONFIG_SYS_I2C_SLAVE1 0x02 153 #define CONFIG_SYS_I2C_SLAVE2 0x02 154 #define CONFIG_SYS_I2C_SLAVE3 0x02 155 #ifndef __ASSEMBLY__ 156 /* Clock supplied to I2C controller in unit of MHz */ 157 unsigned int cm_get_l4_sp_clk_hz(void); 158 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 159 #endif 160 #endif /* CONFIG_DM_I2C */ 161 162 /* 163 * QSPI support 164 */ 165 /* Enable multiple SPI NOR flash manufacturers */ 166 #ifndef CONFIG_SPL_BUILD 167 #define CONFIG_SPI_FLASH_MTD 168 #endif 169 /* QSPI reference clock */ 170 #ifndef __ASSEMBLY__ 171 unsigned int cm_get_qspi_controller_clk_hz(void); 172 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 173 #endif 174 175 /* 176 * Designware SPI support 177 */ 178 179 /* 180 * Serial Driver 181 */ 182 #define CONFIG_SYS_NS16550_SERIAL 183 184 /* 185 * USB 186 */ 187 188 /* 189 * USB Gadget (DFU, UMS) 190 */ 191 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 192 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 193 #define DFU_DEFAULT_POLL_TIMEOUT 300 194 195 /* USB IDs */ 196 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 197 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 198 #endif 199 200 /* 201 * U-Boot environment 202 */ 203 #if !defined(CONFIG_ENV_SIZE) 204 #define CONFIG_ENV_SIZE (8 * 1024) 205 #endif 206 207 /* Environment for SDMMC boot */ 208 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 209 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 210 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 211 #endif 212 213 /* Environment for QSPI boot */ 214 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 215 #define CONFIG_ENV_OFFSET 0x00100000 216 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 217 #endif 218 219 /* 220 * mtd partitioning for serial NOR flash 221 * 222 * device nor0 <ff705000.spi.0>, # parts = 6 223 * #: name size offset mask_flags 224 * 0: u-boot 0x00100000 0x00000000 0 225 * 1: env1 0x00040000 0x00100000 0 226 * 2: env2 0x00040000 0x00140000 0 227 * 3: UBI 0x03e80000 0x00180000 0 228 * 4: boot 0x00e80000 0x00180000 0 229 * 5: rootfs 0x01000000 0x01000000 0 230 * 231 */ 232 233 /* 234 * SPL 235 * 236 * SRAM Memory layout for gen 5: 237 * 238 * 0xFFFF_0000 ...... Start of SRAM 239 * 0xFFFF_xxxx ...... Top of stack (grows down) 240 * 0xFFFF_yyyy ...... Malloc area 241 * 0xFFFF_zzzz ...... Global Data 242 * 0xFFFF_FF00 ...... End of SRAM 243 * 244 * SRAM Memory layout for Arria 10: 245 * 0xFFE0_0000 ...... Start of SRAM (bottom) 246 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 247 * 0xFFEy_yyyy ...... Global Data 248 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 249 * 0xFFE3_FFFF ...... End of SRAM (top) 250 */ 251 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 252 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 253 254 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 255 /* SPL memory allocation configuration, this is for FAT implementation */ 256 #ifndef CONFIG_SYS_SPL_MALLOC_START 257 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 258 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 259 CONFIG_SYS_SPL_MALLOC_SIZE + \ 260 CONFIG_SYS_INIT_RAM_ADDR) 261 #endif 262 #endif 263 264 /* SPL SDMMC boot support */ 265 #ifdef CONFIG_SPL_MMC_SUPPORT 266 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 267 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 268 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 269 #endif 270 #else 271 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 272 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 273 #endif 274 #endif 275 276 /* SPL QSPI boot support */ 277 #ifdef CONFIG_SPL_SPI_SUPPORT 278 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 279 #endif 280 281 /* SPL NAND boot support */ 282 #ifdef CONFIG_SPL_NAND_SUPPORT 283 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 285 #endif 286 287 /* 288 * Stack setup 289 */ 290 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 291 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 292 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 293 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 294 #endif 295 296 /* Extra Environment */ 297 #ifndef CONFIG_SPL_BUILD 298 299 #ifdef CONFIG_CMD_DHCP 300 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 301 #else 302 #define BOOT_TARGET_DEVICES_DHCP(func) 303 #endif 304 305 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 306 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 307 #else 308 #define BOOT_TARGET_DEVICES_PXE(func) 309 #endif 310 311 #ifdef CONFIG_CMD_MMC 312 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 313 #else 314 #define BOOT_TARGET_DEVICES_MMC(func) 315 #endif 316 317 #define BOOT_TARGET_DEVICES(func) \ 318 BOOT_TARGET_DEVICES_MMC(func) \ 319 BOOT_TARGET_DEVICES_PXE(func) \ 320 BOOT_TARGET_DEVICES_DHCP(func) 321 322 #include <config_distro_bootcmd.h> 323 324 #ifndef CONFIG_EXTRA_ENV_SETTINGS 325 #define CONFIG_EXTRA_ENV_SETTINGS \ 326 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 327 "bootm_size=0xa000000\0" \ 328 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 329 "fdt_addr_r=0x02000000\0" \ 330 "scriptaddr=0x02100000\0" \ 331 "pxefile_addr_r=0x02200000\0" \ 332 "ramdisk_addr_r=0x02300000\0" \ 333 BOOTENV 334 335 #endif 336 #endif 337 338 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 339