1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22 /* add target to build it automatically upon "make" */ 23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25 /* 26 * Memory configurations 27 */ 28 #define CONFIG_NR_DRAM_BANKS 1 29 #define PHYS_SDRAM_1 0x0 30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39 #endif 40 #define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 47 #define CONFIG_SYS_TEXT_BASE 0x08000040 48 #else 49 #define CONFIG_SYS_TEXT_BASE 0x01000040 50 #endif 51 52 /* 53 * U-Boot general configurations 54 */ 55 #define CONFIG_SYS_LONGHELP 56 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 57 #define CONFIG_SYS_PBSIZE \ 58 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 59 /* Print buffer size */ 60 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 61 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 62 /* Boot argument buffer size */ 63 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 64 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 65 66 #ifndef CONFIG_SYS_HOSTNAME 67 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 68 #endif 69 70 #define CONFIG_CMD_PXE 71 #define CONFIG_MENU 72 73 /* 74 * Cache 75 */ 76 #define CONFIG_SYS_L2_PL310 77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 78 79 /* 80 * EPCS/EPCQx1 Serial Flash Controller 81 */ 82 #ifdef CONFIG_ALTERA_SPI 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 /* 85 * The base address is configurable in QSys, each board must specify the 86 * base address based on it's particular FPGA configuration. Please note 87 * that the address here is incremented by 0x400 from the Base address 88 * selected in QSys, since the SPI registers are at offset +0x400. 89 * #define CONFIG_SYS_SPI_BASE 0xff240400 90 */ 91 #endif 92 93 /* 94 * Ethernet on SoC (EMAC) 95 */ 96 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 97 #define CONFIG_DW_ALTDESCRIPTOR 98 #define CONFIG_MII 99 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 100 #endif 101 102 /* 103 * FPGA Driver 104 */ 105 #ifdef CONFIG_CMD_FPGA 106 #define CONFIG_FPGA_COUNT 1 107 #endif 108 109 /* 110 * L4 OSC1 Timer 0 111 */ 112 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 113 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 114 #define CONFIG_SYS_TIMER_COUNTS_DOWN 115 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 116 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 117 #define CONFIG_SYS_TIMER_RATE 2400000 118 #else 119 #define CONFIG_SYS_TIMER_RATE 25000000 120 #endif 121 122 /* 123 * L4 Watchdog 124 */ 125 #ifdef CONFIG_HW_WATCHDOG 126 #define CONFIG_DESIGNWARE_WATCHDOG 127 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 128 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 129 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 130 #endif 131 132 /* 133 * MMC Driver 134 */ 135 #ifdef CONFIG_CMD_MMC 136 #define CONFIG_BOUNCE_BUFFER 137 /* FIXME */ 138 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 139 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 140 #endif 141 142 /* 143 * NAND Support 144 */ 145 #ifdef CONFIG_NAND_DENALI 146 #define CONFIG_SYS_MAX_NAND_DEVICE 1 147 #define CONFIG_SYS_NAND_MAX_CHIPS 1 148 #define CONFIG_SYS_NAND_ONFI_DETECTION 149 #define CONFIG_NAND_DENALI_ECC_SIZE 512 150 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 151 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 152 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 153 #endif 154 155 /* 156 * I2C support 157 */ 158 #define CONFIG_SYS_I2C 159 #define CONFIG_SYS_I2C_BUS_MAX 4 160 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 161 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 162 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 163 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 164 /* Using standard mode which the speed up to 100Kb/s */ 165 #define CONFIG_SYS_I2C_SPEED 100000 166 #define CONFIG_SYS_I2C_SPEED1 100000 167 #define CONFIG_SYS_I2C_SPEED2 100000 168 #define CONFIG_SYS_I2C_SPEED3 100000 169 /* Address of device when used as slave */ 170 #define CONFIG_SYS_I2C_SLAVE 0x02 171 #define CONFIG_SYS_I2C_SLAVE1 0x02 172 #define CONFIG_SYS_I2C_SLAVE2 0x02 173 #define CONFIG_SYS_I2C_SLAVE3 0x02 174 #ifndef __ASSEMBLY__ 175 /* Clock supplied to I2C controller in unit of MHz */ 176 unsigned int cm_get_l4_sp_clk_hz(void); 177 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 178 #endif 179 180 /* 181 * QSPI support 182 */ 183 /* Enable multiple SPI NOR flash manufacturers */ 184 #ifndef CONFIG_SPL_BUILD 185 #define CONFIG_SPI_FLASH_MTD 186 #define CONFIG_MTD_DEVICE 187 #define CONFIG_MTD_PARTITIONS 188 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 189 #endif 190 /* QSPI reference clock */ 191 #ifndef __ASSEMBLY__ 192 unsigned int cm_get_qspi_controller_clk_hz(void); 193 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 194 #endif 195 #define CONFIG_CQSPI_DECODER 0 196 #define CONFIG_BOUNCE_BUFFER 197 198 /* 199 * Designware SPI support 200 */ 201 202 /* 203 * Serial Driver 204 */ 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE -4 207 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 208 #define CONFIG_SYS_NS16550_CLK 1000000 209 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 210 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 211 #define CONFIG_SYS_NS16550_CLK 100000000 212 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 213 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 214 #define CONFIG_SYS_NS16550_CLK 50000000 215 #endif 216 #define CONFIG_CONS_INDEX 1 217 218 /* 219 * USB 220 */ 221 222 /* 223 * USB Gadget (DFU, UMS) 224 */ 225 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 226 #define CONFIG_USB_FUNCTION_MASS_STORAGE 227 228 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 229 #define DFU_DEFAULT_POLL_TIMEOUT 300 230 231 /* USB IDs */ 232 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 233 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 234 #endif 235 236 /* 237 * U-Boot environment 238 */ 239 #if !defined(CONFIG_ENV_SIZE) 240 #define CONFIG_ENV_SIZE (8 * 1024) 241 #endif 242 243 /* Environment for SDMMC boot */ 244 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 245 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 246 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 247 #endif 248 249 /* Environment for QSPI boot */ 250 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 251 #define CONFIG_ENV_OFFSET 0x00100000 252 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 253 #endif 254 255 /* 256 * mtd partitioning for serial NOR flash 257 * 258 * device nor0 <ff705000.spi.0>, # parts = 6 259 * #: name size offset mask_flags 260 * 0: u-boot 0x00100000 0x00000000 0 261 * 1: env1 0x00040000 0x00100000 0 262 * 2: env2 0x00040000 0x00140000 0 263 * 3: UBI 0x03e80000 0x00180000 0 264 * 4: boot 0x00e80000 0x00180000 0 265 * 5: rootfs 0x01000000 0x01000000 0 266 * 267 */ 268 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 269 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 270 "1m(u-boot)," \ 271 "256k(env1)," \ 272 "256k(env2)," \ 273 "14848k(boot)," \ 274 "16m(rootfs)," \ 275 "-@1536k(UBI)\0" 276 #endif 277 278 /* 279 * SPL 280 * 281 * SRAM Memory layout: 282 * 283 * 0xFFFF_0000 ...... Start of SRAM 284 * 0xFFFF_xxxx ...... Top of stack (grows down) 285 * 0xFFFF_yyyy ...... Malloc area 286 * 0xFFFF_zzzz ...... Global Data 287 * 0xFFFF_FF00 ...... End of SRAM 288 */ 289 #define CONFIG_SPL_FRAMEWORK 290 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 291 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 292 293 /* SPL SDMMC boot support */ 294 #ifdef CONFIG_SPL_MMC_SUPPORT 295 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 296 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 297 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 298 #endif 299 #else 300 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 301 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 302 #endif 303 #endif 304 305 /* SPL QSPI boot support */ 306 #ifdef CONFIG_SPL_SPI_SUPPORT 307 #define CONFIG_SPL_SPI_LOAD 308 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 309 #endif 310 311 /* SPL NAND boot support */ 312 #ifdef CONFIG_SPL_NAND_SUPPORT 313 #define CONFIG_SYS_NAND_USE_FLASH_BBT 314 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 315 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 316 #endif 317 318 /* 319 * Stack setup 320 */ 321 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 322 323 /* Extra Environment */ 324 #ifndef CONFIG_SPL_BUILD 325 #include <config_distro_defaults.h> 326 327 #ifdef CONFIG_CMD_PXE 328 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 329 #else 330 #define BOOT_TARGET_DEVICES_PXE(func) 331 #endif 332 333 #ifdef CONFIG_CMD_MMC 334 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 335 #else 336 #define BOOT_TARGET_DEVICES_MMC(func) 337 #endif 338 339 #define BOOT_TARGET_DEVICES(func) \ 340 BOOT_TARGET_DEVICES_MMC(func) \ 341 BOOT_TARGET_DEVICES_PXE(func) \ 342 func(DHCP, dhcp, na) 343 344 #include <config_distro_bootcmd.h> 345 346 #ifndef CONFIG_EXTRA_ENV_SETTINGS 347 #define CONFIG_EXTRA_ENV_SETTINGS \ 348 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 349 "bootm_size=0xa000000\0" \ 350 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 351 "fdt_addr_r=0x02000000\0" \ 352 "scriptaddr=0x02100000\0" \ 353 "pxefile_addr_r=0x02200000\0" \ 354 "ramdisk_addr_r=0x02300000\0" \ 355 BOOTENV 356 357 #endif 358 #endif 359 360 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 361