1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* add target to build it automatically upon "make" */ 18 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 19 20 /* 21 * Memory configurations 22 */ 23 #define PHYS_SDRAM_1 0x0 24 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 25 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 26 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 27 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 29 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 30 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 31 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 32 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 33 #endif 34 #define CONFIG_SYS_INIT_SP_ADDR \ 35 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 36 37 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 38 39 /* 40 * U-Boot general configurations 41 */ 42 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 43 /* Print buffer size */ 44 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 45 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 46 /* Boot argument buffer size */ 47 48 #ifndef CONFIG_SYS_HOSTNAME 49 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 50 #endif 51 52 /* 53 * Cache 54 */ 55 #define CONFIG_SYS_L2_PL310 56 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 57 58 /* 59 * EPCS/EPCQx1 Serial Flash Controller 60 */ 61 #ifdef CONFIG_ALTERA_SPI 62 #define CONFIG_SF_DEFAULT_SPEED 30000000 63 /* 64 * The base address is configurable in QSys, each board must specify the 65 * base address based on it's particular FPGA configuration. Please note 66 * that the address here is incremented by 0x400 from the Base address 67 * selected in QSys, since the SPI registers are at offset +0x400. 68 * #define CONFIG_SYS_SPI_BASE 0xff240400 69 */ 70 #endif 71 72 /* 73 * Ethernet on SoC (EMAC) 74 */ 75 #ifdef CONFIG_CMD_NET 76 #define CONFIG_DW_ALTDESCRIPTOR 77 #endif 78 79 /* 80 * FPGA Driver 81 */ 82 #ifdef CONFIG_CMD_FPGA 83 #define CONFIG_FPGA_COUNT 1 84 #endif 85 86 /* 87 * L4 OSC1 Timer 0 88 */ 89 #ifndef CONFIG_TIMER 90 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 91 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 92 #define CONFIG_SYS_TIMER_COUNTS_DOWN 93 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 94 #define CONFIG_SYS_TIMER_RATE 25000000 95 #endif 96 97 /* 98 * L4 Watchdog 99 */ 100 #ifdef CONFIG_HW_WATCHDOG 101 #define CONFIG_DESIGNWARE_WATCHDOG 102 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 103 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 104 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 105 #endif 106 107 /* 108 * MMC Driver 109 */ 110 #ifdef CONFIG_CMD_MMC 111 #define CONFIG_BOUNCE_BUFFER 112 /* FIXME */ 113 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 114 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 115 #endif 116 117 /* 118 * NAND Support 119 */ 120 #ifdef CONFIG_NAND_DENALI 121 #define CONFIG_SYS_MAX_NAND_DEVICE 1 122 #define CONFIG_SYS_NAND_ONFI_DETECTION 123 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 124 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 125 #endif 126 127 /* 128 * I2C support 129 */ 130 #ifndef CONFIG_DM_I2C 131 #define CONFIG_SYS_I2C 132 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 133 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 134 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 135 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 136 /* Using standard mode which the speed up to 100Kb/s */ 137 #define CONFIG_SYS_I2C_SPEED 100000 138 #define CONFIG_SYS_I2C_SPEED1 100000 139 #define CONFIG_SYS_I2C_SPEED2 100000 140 #define CONFIG_SYS_I2C_SPEED3 100000 141 /* Address of device when used as slave */ 142 #define CONFIG_SYS_I2C_SLAVE 0x02 143 #define CONFIG_SYS_I2C_SLAVE1 0x02 144 #define CONFIG_SYS_I2C_SLAVE2 0x02 145 #define CONFIG_SYS_I2C_SLAVE3 0x02 146 #ifndef __ASSEMBLY__ 147 /* Clock supplied to I2C controller in unit of MHz */ 148 unsigned int cm_get_l4_sp_clk_hz(void); 149 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 150 #endif 151 #endif /* CONFIG_DM_I2C */ 152 153 /* 154 * QSPI support 155 */ 156 /* Enable multiple SPI NOR flash manufacturers */ 157 #ifndef CONFIG_SPL_BUILD 158 #define CONFIG_SPI_FLASH_MTD 159 #endif 160 /* QSPI reference clock */ 161 #ifndef __ASSEMBLY__ 162 unsigned int cm_get_qspi_controller_clk_hz(void); 163 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 164 #endif 165 166 /* 167 * Designware SPI support 168 */ 169 170 /* 171 * Serial Driver 172 */ 173 #define CONFIG_SYS_NS16550_SERIAL 174 175 /* 176 * USB 177 */ 178 179 /* 180 * USB Gadget (DFU, UMS) 181 */ 182 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 183 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 184 #define DFU_DEFAULT_POLL_TIMEOUT 300 185 186 /* USB IDs */ 187 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 188 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 189 #endif 190 191 /* 192 * U-Boot environment 193 */ 194 #if !defined(CONFIG_ENV_SIZE) 195 #define CONFIG_ENV_SIZE (8 * 1024) 196 #endif 197 198 /* Environment for SDMMC boot */ 199 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 200 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 201 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 202 #endif 203 204 /* Environment for QSPI boot */ 205 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 206 #define CONFIG_ENV_OFFSET 0x00100000 207 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 208 #endif 209 210 /* 211 * mtd partitioning for serial NOR flash 212 * 213 * device nor0 <ff705000.spi.0>, # parts = 6 214 * #: name size offset mask_flags 215 * 0: u-boot 0x00100000 0x00000000 0 216 * 1: env1 0x00040000 0x00100000 0 217 * 2: env2 0x00040000 0x00140000 0 218 * 3: UBI 0x03e80000 0x00180000 0 219 * 4: boot 0x00e80000 0x00180000 0 220 * 5: rootfs 0x01000000 0x01000000 0 221 * 222 */ 223 224 /* 225 * SPL 226 * 227 * SRAM Memory layout for gen 5: 228 * 229 * 0xFFFF_0000 ...... Start of SRAM 230 * 0xFFFF_xxxx ...... Top of stack (grows down) 231 * 0xFFFF_yyyy ...... Malloc area 232 * 0xFFFF_zzzz ...... Global Data 233 * 0xFFFF_FF00 ...... End of SRAM 234 * 235 * SRAM Memory layout for Arria 10: 236 * 0xFFE0_0000 ...... Start of SRAM (bottom) 237 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 238 * 0xFFEy_yyyy ...... Global Data 239 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 240 * 0xFFE3_FFFF ...... End of SRAM (top) 241 */ 242 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 243 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 244 245 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 246 /* SPL memory allocation configuration, this is for FAT implementation */ 247 #ifndef CONFIG_SYS_SPL_MALLOC_START 248 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 249 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 250 CONFIG_SYS_SPL_MALLOC_SIZE + \ 251 CONFIG_SYS_INIT_RAM_ADDR) 252 #endif 253 #endif 254 255 /* SPL SDMMC boot support */ 256 #ifdef CONFIG_SPL_MMC_SUPPORT 257 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 258 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 259 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 260 #endif 261 #else 262 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 263 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 264 #endif 265 #endif 266 267 /* SPL QSPI boot support */ 268 #ifdef CONFIG_SPL_SPI_SUPPORT 269 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 270 #endif 271 272 /* SPL NAND boot support */ 273 #ifdef CONFIG_SPL_NAND_SUPPORT 274 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 275 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 276 #endif 277 278 /* 279 * Stack setup 280 */ 281 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 282 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 283 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 284 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 285 #endif 286 287 /* Extra Environment */ 288 #ifndef CONFIG_SPL_BUILD 289 290 #ifdef CONFIG_CMD_DHCP 291 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 292 #else 293 #define BOOT_TARGET_DEVICES_DHCP(func) 294 #endif 295 296 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 297 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 298 #else 299 #define BOOT_TARGET_DEVICES_PXE(func) 300 #endif 301 302 #ifdef CONFIG_CMD_MMC 303 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 304 #else 305 #define BOOT_TARGET_DEVICES_MMC(func) 306 #endif 307 308 #define BOOT_TARGET_DEVICES(func) \ 309 BOOT_TARGET_DEVICES_MMC(func) \ 310 BOOT_TARGET_DEVICES_PXE(func) \ 311 BOOT_TARGET_DEVICES_DHCP(func) 312 313 #include <config_distro_bootcmd.h> 314 315 #ifndef CONFIG_EXTRA_ENV_SETTINGS 316 #define CONFIG_EXTRA_ENV_SETTINGS \ 317 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 318 "bootm_size=0xa000000\0" \ 319 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 320 "fdt_addr_r=0x02000000\0" \ 321 "scriptaddr=0x02100000\0" \ 322 "pxefile_addr_r=0x02200000\0" \ 323 "ramdisk_addr_r=0x02300000\0" \ 324 BOOTENV 325 326 #endif 327 #endif 328 329 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 330