1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* add target to build it automatically upon "make" */ 18 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 19 20 /* 21 * Memory configurations 22 */ 23 #define PHYS_SDRAM_1 0x0 24 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 25 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 26 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 27 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 29 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 30 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 31 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 32 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 33 #endif 34 35 /* 36 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 37 * SRAM as bootcounter storage. Make sure to not put the stack directly 38 * at this address to not overwrite the bootcounter by checking, if the 39 * bootcounter address is located in the internal SRAM. 40 */ 41 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 42 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 43 CONFIG_SYS_INIT_RAM_SIZE))) 44 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR 45 #else 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 48 #endif 49 50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 52 /* 53 * U-Boot general configurations 54 */ 55 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 56 /* Print buffer size */ 57 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 58 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 59 /* Boot argument buffer size */ 60 61 #ifndef CONFIG_SYS_HOSTNAME 62 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 63 #endif 64 65 /* 66 * Cache 67 */ 68 #define CONFIG_SYS_L2_PL310 69 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 70 71 /* 72 * EPCS/EPCQx1 Serial Flash Controller 73 */ 74 #ifdef CONFIG_ALTERA_SPI 75 #define CONFIG_SF_DEFAULT_SPEED 30000000 76 /* 77 * The base address is configurable in QSys, each board must specify the 78 * base address based on it's particular FPGA configuration. Please note 79 * that the address here is incremented by 0x400 from the Base address 80 * selected in QSys, since the SPI registers are at offset +0x400. 81 * #define CONFIG_SYS_SPI_BASE 0xff240400 82 */ 83 #endif 84 85 /* 86 * Ethernet on SoC (EMAC) 87 */ 88 #ifdef CONFIG_CMD_NET 89 #define CONFIG_DW_ALTDESCRIPTOR 90 #endif 91 92 /* 93 * FPGA Driver 94 */ 95 #ifdef CONFIG_CMD_FPGA 96 #define CONFIG_FPGA_COUNT 1 97 #endif 98 99 /* 100 * L4 OSC1 Timer 0 101 */ 102 #ifndef CONFIG_TIMER 103 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 104 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 105 #define CONFIG_SYS_TIMER_COUNTS_DOWN 106 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 107 #define CONFIG_SYS_TIMER_RATE 25000000 108 #endif 109 110 /* 111 * L4 Watchdog 112 */ 113 #ifdef CONFIG_HW_WATCHDOG 114 #define CONFIG_DESIGNWARE_WATCHDOG 115 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 116 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 117 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 118 #endif 119 120 /* 121 * MMC Driver 122 */ 123 #ifdef CONFIG_CMD_MMC 124 /* FIXME */ 125 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 126 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 127 #endif 128 129 /* 130 * NAND Support 131 */ 132 #ifdef CONFIG_NAND_DENALI 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 134 #define CONFIG_SYS_NAND_ONFI_DETECTION 135 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 136 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 137 #endif 138 139 /* 140 * I2C support 141 */ 142 #ifndef CONFIG_DM_I2C 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 145 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 146 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 147 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 148 /* Using standard mode which the speed up to 100Kb/s */ 149 #define CONFIG_SYS_I2C_SPEED 100000 150 #define CONFIG_SYS_I2C_SPEED1 100000 151 #define CONFIG_SYS_I2C_SPEED2 100000 152 #define CONFIG_SYS_I2C_SPEED3 100000 153 /* Address of device when used as slave */ 154 #define CONFIG_SYS_I2C_SLAVE 0x02 155 #define CONFIG_SYS_I2C_SLAVE1 0x02 156 #define CONFIG_SYS_I2C_SLAVE2 0x02 157 #define CONFIG_SYS_I2C_SLAVE3 0x02 158 #ifndef __ASSEMBLY__ 159 /* Clock supplied to I2C controller in unit of MHz */ 160 unsigned int cm_get_l4_sp_clk_hz(void); 161 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 162 #endif 163 #endif /* CONFIG_DM_I2C */ 164 165 /* 166 * QSPI support 167 */ 168 /* Enable multiple SPI NOR flash manufacturers */ 169 #ifndef CONFIG_SPL_BUILD 170 #define CONFIG_SPI_FLASH_MTD 171 #endif 172 /* QSPI reference clock */ 173 #ifndef __ASSEMBLY__ 174 unsigned int cm_get_qspi_controller_clk_hz(void); 175 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 176 #endif 177 178 /* 179 * Designware SPI support 180 */ 181 182 /* 183 * Serial Driver 184 */ 185 #define CONFIG_SYS_NS16550_SERIAL 186 187 /* 188 * USB 189 */ 190 191 /* 192 * USB Gadget (DFU, UMS) 193 */ 194 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 195 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 196 #define DFU_DEFAULT_POLL_TIMEOUT 300 197 198 /* USB IDs */ 199 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 200 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 201 #endif 202 203 /* 204 * U-Boot environment 205 */ 206 #if !defined(CONFIG_ENV_SIZE) 207 #define CONFIG_ENV_SIZE (8 * 1024) 208 #endif 209 210 /* Environment for SDMMC boot */ 211 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 212 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 213 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 214 #endif 215 216 /* Environment for QSPI boot */ 217 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 218 #define CONFIG_ENV_OFFSET 0x00100000 219 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 220 #endif 221 222 /* 223 * mtd partitioning for serial NOR flash 224 * 225 * device nor0 <ff705000.spi.0>, # parts = 6 226 * #: name size offset mask_flags 227 * 0: u-boot 0x00100000 0x00000000 0 228 * 1: env1 0x00040000 0x00100000 0 229 * 2: env2 0x00040000 0x00140000 0 230 * 3: UBI 0x03e80000 0x00180000 0 231 * 4: boot 0x00e80000 0x00180000 0 232 * 5: rootfs 0x01000000 0x01000000 0 233 * 234 */ 235 236 /* 237 * SPL 238 * 239 * SRAM Memory layout for gen 5: 240 * 241 * 0xFFFF_0000 ...... Start of SRAM 242 * 0xFFFF_xxxx ...... Top of stack (grows down) 243 * 0xFFFF_yyyy ...... Malloc area 244 * 0xFFFF_zzzz ...... Global Data 245 * 0xFFFF_FF00 ...... End of SRAM 246 * 247 * SRAM Memory layout for Arria 10: 248 * 0xFFE0_0000 ...... Start of SRAM (bottom) 249 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 250 * 0xFFEy_yyyy ...... Global Data 251 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 252 * 0xFFE3_FFFF ...... End of SRAM (top) 253 */ 254 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 255 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 256 257 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 258 /* SPL memory allocation configuration, this is for FAT implementation */ 259 #ifndef CONFIG_SYS_SPL_MALLOC_START 260 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 261 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 262 CONFIG_SYS_SPL_MALLOC_SIZE + \ 263 CONFIG_SYS_INIT_RAM_ADDR) 264 #endif 265 #endif 266 267 /* SPL SDMMC boot support */ 268 #ifdef CONFIG_SPL_MMC_SUPPORT 269 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 270 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 271 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 272 #endif 273 #else 274 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 275 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 276 #endif 277 #endif 278 279 /* SPL QSPI boot support */ 280 #ifdef CONFIG_SPL_SPI_SUPPORT 281 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 282 #endif 283 284 /* SPL NAND boot support */ 285 #ifdef CONFIG_SPL_NAND_SUPPORT 286 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 287 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 288 #endif 289 290 /* 291 * Stack setup 292 */ 293 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 294 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 295 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 296 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 297 #endif 298 299 /* Extra Environment */ 300 #ifndef CONFIG_SPL_BUILD 301 302 #ifdef CONFIG_CMD_DHCP 303 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 304 #else 305 #define BOOT_TARGET_DEVICES_DHCP(func) 306 #endif 307 308 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 309 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 310 #else 311 #define BOOT_TARGET_DEVICES_PXE(func) 312 #endif 313 314 #ifdef CONFIG_CMD_MMC 315 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 316 #else 317 #define BOOT_TARGET_DEVICES_MMC(func) 318 #endif 319 320 #define BOOT_TARGET_DEVICES(func) \ 321 BOOT_TARGET_DEVICES_MMC(func) \ 322 BOOT_TARGET_DEVICES_PXE(func) \ 323 BOOT_TARGET_DEVICES_DHCP(func) 324 325 #include <config_distro_bootcmd.h> 326 327 #ifndef CONFIG_EXTRA_ENV_SETTINGS 328 #define CONFIG_EXTRA_ENV_SETTINGS \ 329 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 330 "bootm_size=0xa000000\0" \ 331 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 332 "fdt_addr_r=0x02000000\0" \ 333 "scriptaddr=0x02100000\0" \ 334 "pxefile_addr_r=0x02200000\0" \ 335 "ramdisk_addr_r=0x02300000\0" \ 336 BOOTENV 337 338 #endif 339 #endif 340 341 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 342