1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* add target to build it automatically upon "make" */ 18 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 19 20 /* 21 * Memory configurations 22 */ 23 #define CONFIG_NR_DRAM_BANKS 1 24 #define PHYS_SDRAM_1 0x0 25 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 26 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 27 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 28 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 29 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 30 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 31 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 33 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 34 #endif 35 #define CONFIG_SYS_INIT_SP_ADDR \ 36 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 37 38 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 39 40 /* 41 * U-Boot general configurations 42 */ 43 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 44 /* Print buffer size */ 45 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 46 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 47 /* Boot argument buffer size */ 48 49 #ifndef CONFIG_SYS_HOSTNAME 50 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 51 #endif 52 53 /* 54 * Cache 55 */ 56 #define CONFIG_SYS_L2_PL310 57 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 58 59 /* 60 * EPCS/EPCQx1 Serial Flash Controller 61 */ 62 #ifdef CONFIG_ALTERA_SPI 63 #define CONFIG_SF_DEFAULT_SPEED 30000000 64 /* 65 * The base address is configurable in QSys, each board must specify the 66 * base address based on it's particular FPGA configuration. Please note 67 * that the address here is incremented by 0x400 from the Base address 68 * selected in QSys, since the SPI registers are at offset +0x400. 69 * #define CONFIG_SYS_SPI_BASE 0xff240400 70 */ 71 #endif 72 73 /* 74 * Ethernet on SoC (EMAC) 75 */ 76 #ifdef CONFIG_CMD_NET 77 #define CONFIG_DW_ALTDESCRIPTOR 78 #define CONFIG_MII 79 #endif 80 81 /* 82 * FPGA Driver 83 */ 84 #ifdef CONFIG_CMD_FPGA 85 #define CONFIG_FPGA_COUNT 1 86 #endif 87 88 /* 89 * L4 OSC1 Timer 0 90 */ 91 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 92 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 93 #define CONFIG_SYS_TIMER_COUNTS_DOWN 94 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 95 #define CONFIG_SYS_TIMER_RATE 25000000 96 97 /* 98 * L4 Watchdog 99 */ 100 #ifdef CONFIG_HW_WATCHDOG 101 #define CONFIG_DESIGNWARE_WATCHDOG 102 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 103 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 104 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 105 #endif 106 107 /* 108 * MMC Driver 109 */ 110 #ifdef CONFIG_CMD_MMC 111 #define CONFIG_BOUNCE_BUFFER 112 /* FIXME */ 113 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 114 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 115 #endif 116 117 /* 118 * NAND Support 119 */ 120 #ifdef CONFIG_NAND_DENALI 121 #define CONFIG_SYS_MAX_NAND_DEVICE 1 122 #define CONFIG_SYS_NAND_ONFI_DETECTION 123 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 124 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 125 #endif 126 127 /* 128 * I2C support 129 */ 130 #ifndef CONFIG_DM_I2C 131 #define CONFIG_SYS_I2C 132 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 133 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 134 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 135 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 136 /* Using standard mode which the speed up to 100Kb/s */ 137 #define CONFIG_SYS_I2C_SPEED 100000 138 #define CONFIG_SYS_I2C_SPEED1 100000 139 #define CONFIG_SYS_I2C_SPEED2 100000 140 #define CONFIG_SYS_I2C_SPEED3 100000 141 /* Address of device when used as slave */ 142 #define CONFIG_SYS_I2C_SLAVE 0x02 143 #define CONFIG_SYS_I2C_SLAVE1 0x02 144 #define CONFIG_SYS_I2C_SLAVE2 0x02 145 #define CONFIG_SYS_I2C_SLAVE3 0x02 146 #ifndef __ASSEMBLY__ 147 /* Clock supplied to I2C controller in unit of MHz */ 148 unsigned int cm_get_l4_sp_clk_hz(void); 149 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 150 #endif 151 #endif /* CONFIG_DM_I2C */ 152 153 /* 154 * QSPI support 155 */ 156 /* Enable multiple SPI NOR flash manufacturers */ 157 #ifndef CONFIG_SPL_BUILD 158 #define CONFIG_SPI_FLASH_MTD 159 #define CONFIG_MTD_DEVICE 160 #define CONFIG_MTD_PARTITIONS 161 #endif 162 /* QSPI reference clock */ 163 #ifndef __ASSEMBLY__ 164 unsigned int cm_get_qspi_controller_clk_hz(void); 165 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 166 #endif 167 168 /* 169 * Designware SPI support 170 */ 171 172 /* 173 * Serial Driver 174 */ 175 #define CONFIG_SYS_NS16550_SERIAL 176 177 /* 178 * USB 179 */ 180 181 /* 182 * USB Gadget (DFU, UMS) 183 */ 184 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 185 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 186 #define DFU_DEFAULT_POLL_TIMEOUT 300 187 188 /* USB IDs */ 189 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 190 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 191 #endif 192 193 /* 194 * U-Boot environment 195 */ 196 #if !defined(CONFIG_ENV_SIZE) 197 #define CONFIG_ENV_SIZE (8 * 1024) 198 #endif 199 200 /* Environment for SDMMC boot */ 201 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 202 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 203 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 204 #endif 205 206 /* Environment for QSPI boot */ 207 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 208 #define CONFIG_ENV_OFFSET 0x00100000 209 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 210 #endif 211 212 /* 213 * mtd partitioning for serial NOR flash 214 * 215 * device nor0 <ff705000.spi.0>, # parts = 6 216 * #: name size offset mask_flags 217 * 0: u-boot 0x00100000 0x00000000 0 218 * 1: env1 0x00040000 0x00100000 0 219 * 2: env2 0x00040000 0x00140000 0 220 * 3: UBI 0x03e80000 0x00180000 0 221 * 4: boot 0x00e80000 0x00180000 0 222 * 5: rootfs 0x01000000 0x01000000 0 223 * 224 */ 225 226 /* 227 * SPL 228 * 229 * SRAM Memory layout for gen 5: 230 * 231 * 0xFFFF_0000 ...... Start of SRAM 232 * 0xFFFF_xxxx ...... Top of stack (grows down) 233 * 0xFFFF_yyyy ...... Malloc area 234 * 0xFFFF_zzzz ...... Global Data 235 * 0xFFFF_FF00 ...... End of SRAM 236 * 237 * SRAM Memory layout for Arria 10: 238 * 0xFFE0_0000 ...... Start of SRAM (bottom) 239 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 240 * 0xFFEy_yyyy ...... Global Data 241 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 242 * 0xFFE3_FFFF ...... End of SRAM (top) 243 */ 244 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 245 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 246 247 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 248 /* SPL memory allocation configuration, this is for FAT implementation */ 249 #ifndef CONFIG_SYS_SPL_MALLOC_START 250 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 251 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 252 CONFIG_SYS_SPL_MALLOC_SIZE + \ 253 CONFIG_SYS_INIT_RAM_ADDR) 254 #endif 255 #endif 256 257 /* SPL SDMMC boot support */ 258 #ifdef CONFIG_SPL_MMC_SUPPORT 259 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 260 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 261 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 262 #endif 263 #else 264 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 265 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 266 #endif 267 #endif 268 269 /* SPL QSPI boot support */ 270 #ifdef CONFIG_SPL_SPI_SUPPORT 271 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 272 #endif 273 274 /* SPL NAND boot support */ 275 #ifdef CONFIG_SPL_NAND_SUPPORT 276 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 277 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 278 #endif 279 280 /* 281 * Stack setup 282 */ 283 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 284 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 285 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 286 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 287 #endif 288 289 /* Extra Environment */ 290 #ifndef CONFIG_SPL_BUILD 291 292 #ifdef CONFIG_CMD_DHCP 293 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 294 #else 295 #define BOOT_TARGET_DEVICES_DHCP(func) 296 #endif 297 298 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 299 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 300 #else 301 #define BOOT_TARGET_DEVICES_PXE(func) 302 #endif 303 304 #ifdef CONFIG_CMD_MMC 305 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 306 #else 307 #define BOOT_TARGET_DEVICES_MMC(func) 308 #endif 309 310 #define BOOT_TARGET_DEVICES(func) \ 311 BOOT_TARGET_DEVICES_MMC(func) \ 312 BOOT_TARGET_DEVICES_PXE(func) \ 313 BOOT_TARGET_DEVICES_DHCP(func) 314 315 #include <config_distro_bootcmd.h> 316 317 #ifndef CONFIG_EXTRA_ENV_SETTINGS 318 #define CONFIG_EXTRA_ENV_SETTINGS \ 319 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 320 "bootm_size=0xa000000\0" \ 321 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 322 "fdt_addr_r=0x02000000\0" \ 323 "scriptaddr=0x02100000\0" \ 324 "pxefile_addr_r=0x02200000\0" \ 325 "ramdisk_addr_r=0x02300000\0" \ 326 BOOTENV 327 328 #endif 329 #endif 330 331 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 332