1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 #define CONFIG_SYS_THUMB_BUILD 13 14 /* 15 * High level configuration 16 */ 17 #define CONFIG_DISPLAY_CPUINFO 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 #define CONFIG_ARCH_MISC_INIT 20 #define CONFIG_ARCH_EARLY_INIT_R 21 #define CONFIG_SYS_NO_FLASH 22 #define CONFIG_CLOCKS 23 24 #define CONFIG_CRC32_VERIFY 25 26 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* add target to build it automatically upon "make" */ 31 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 32 33 /* 34 * Memory configurations 35 */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define PHYS_SDRAM_1 0x0 38 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 39 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 40 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 41 42 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 43 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 44 #define CONFIG_SYS_INIT_SP_OFFSET \ 45 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 48 49 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 51 #define CONFIG_SYS_TEXT_BASE 0x08000040 52 #else 53 #define CONFIG_SYS_TEXT_BASE 0x01000040 54 #endif 55 56 /* 57 * U-Boot general configurations 58 */ 59 #define CONFIG_SYS_LONGHELP 60 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 61 #define CONFIG_SYS_PBSIZE \ 62 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 63 /* Print buffer size */ 64 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 65 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 66 /* Boot argument buffer size */ 67 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 68 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 69 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 70 71 #ifndef CONFIG_SYS_HOSTNAME 72 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 73 #endif 74 75 /* 76 * Cache 77 */ 78 #define CONFIG_SYS_L2_PL310 79 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 80 81 /* 82 * SDRAM controller 83 */ 84 #define CONFIG_ALTERA_SDRAM 85 86 /* 87 * EPCS/EPCQx1 Serial Flash Controller 88 */ 89 #ifdef CONFIG_ALTERA_SPI 90 #define CONFIG_SF_DEFAULT_SPEED 30000000 91 /* 92 * The base address is configurable in QSys, each board must specify the 93 * base address based on it's particular FPGA configuration. Please note 94 * that the address here is incremented by 0x400 from the Base address 95 * selected in QSys, since the SPI registers are at offset +0x400. 96 * #define CONFIG_SYS_SPI_BASE 0xff240400 97 */ 98 #endif 99 100 /* 101 * Ethernet on SoC (EMAC) 102 */ 103 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 104 #define CONFIG_DW_ALTDESCRIPTOR 105 #define CONFIG_MII 106 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 107 #define CONFIG_PHY_GIGE 108 #endif 109 110 /* 111 * FPGA Driver 112 */ 113 #ifdef CONFIG_CMD_FPGA 114 #define CONFIG_FPGA 115 #define CONFIG_FPGA_ALTERA 116 #define CONFIG_FPGA_SOCFPGA 117 #define CONFIG_FPGA_COUNT 1 118 #endif 119 120 /* 121 * L4 OSC1 Timer 0 122 */ 123 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 124 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 125 #define CONFIG_SYS_TIMER_COUNTS_DOWN 126 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 127 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 128 #define CONFIG_SYS_TIMER_RATE 2400000 129 #else 130 #define CONFIG_SYS_TIMER_RATE 25000000 131 #endif 132 133 /* 134 * L4 Watchdog 135 */ 136 #ifdef CONFIG_HW_WATCHDOG 137 #define CONFIG_DESIGNWARE_WATCHDOG 138 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 139 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 140 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 141 #endif 142 143 /* 144 * MMC Driver 145 */ 146 #ifdef CONFIG_CMD_MMC 147 #define CONFIG_MMC 148 #define CONFIG_BOUNCE_BUFFER 149 #define CONFIG_GENERIC_MMC 150 #define CONFIG_DWMMC 151 #define CONFIG_SOCFPGA_DWMMC 152 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 153 /* FIXME */ 154 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 155 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 156 #endif 157 158 /* 159 * NAND Support 160 */ 161 #ifdef CONFIG_NAND_DENALI 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 163 #define CONFIG_SYS_NAND_MAX_CHIPS 1 164 #define CONFIG_SYS_NAND_ONFI_DETECTION 165 #define CONFIG_NAND_DENALI_ECC_SIZE 512 166 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 167 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 168 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 169 #endif 170 171 /* 172 * I2C support 173 */ 174 #define CONFIG_SYS_I2C 175 #define CONFIG_SYS_I2C_BUS_MAX 4 176 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 177 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 178 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 179 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 180 /* Using standard mode which the speed up to 100Kb/s */ 181 #define CONFIG_SYS_I2C_SPEED 100000 182 #define CONFIG_SYS_I2C_SPEED1 100000 183 #define CONFIG_SYS_I2C_SPEED2 100000 184 #define CONFIG_SYS_I2C_SPEED3 100000 185 /* Address of device when used as slave */ 186 #define CONFIG_SYS_I2C_SLAVE 0x02 187 #define CONFIG_SYS_I2C_SLAVE1 0x02 188 #define CONFIG_SYS_I2C_SLAVE2 0x02 189 #define CONFIG_SYS_I2C_SLAVE3 0x02 190 #ifndef __ASSEMBLY__ 191 /* Clock supplied to I2C controller in unit of MHz */ 192 unsigned int cm_get_l4_sp_clk_hz(void); 193 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 194 #endif 195 196 /* 197 * QSPI support 198 */ 199 /* Enable multiple SPI NOR flash manufacturers */ 200 #ifndef CONFIG_SPL_BUILD 201 #define CONFIG_SPI_FLASH_MTD 202 #define CONFIG_CMD_MTDPARTS 203 #define CONFIG_MTD_DEVICE 204 #define CONFIG_MTD_PARTITIONS 205 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 206 #endif 207 /* QSPI reference clock */ 208 #ifndef __ASSEMBLY__ 209 unsigned int cm_get_qspi_controller_clk_hz(void); 210 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 211 #endif 212 #define CONFIG_CQSPI_DECODER 0 213 214 /* 215 * Designware SPI support 216 */ 217 218 /* 219 * Serial Driver 220 */ 221 #define CONFIG_SYS_NS16550_SERIAL 222 #define CONFIG_SYS_NS16550_REG_SIZE -4 223 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 224 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 225 #define CONFIG_SYS_NS16550_CLK 1000000 226 #else 227 #define CONFIG_SYS_NS16550_CLK 100000000 228 #endif 229 #define CONFIG_CONS_INDEX 1 230 #define CONFIG_BAUDRATE 115200 231 232 /* 233 * USB 234 */ 235 #ifdef CONFIG_CMD_USB 236 #define CONFIG_USB_DWC2 237 #define CONFIG_USB_STORAGE 238 #endif 239 240 /* 241 * USB Gadget (DFU, UMS) 242 */ 243 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 244 #define CONFIG_USB_FUNCTION_MASS_STORAGE 245 246 #define CONFIG_USB_FUNCTION_DFU 247 #ifdef CONFIG_DM_MMC 248 #define CONFIG_DFU_MMC 249 #endif 250 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 251 #define DFU_DEFAULT_POLL_TIMEOUT 300 252 253 /* USB IDs */ 254 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 255 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 256 #endif 257 258 /* 259 * U-Boot environment 260 */ 261 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 262 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 263 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 264 #if !defined(CONFIG_ENV_SIZE) 265 #define CONFIG_ENV_SIZE 4096 266 #endif 267 268 /* Environment for SDMMC boot */ 269 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 270 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 271 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 272 #endif 273 274 /* Environment for QSPI boot */ 275 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 276 #define CONFIG_ENV_OFFSET 0x00100000 277 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 278 #endif 279 280 /* 281 * mtd partitioning for serial NOR flash 282 * 283 * device nor0 <ff705000.spi.0>, # parts = 6 284 * #: name size offset mask_flags 285 * 0: u-boot 0x00100000 0x00000000 0 286 * 1: env1 0x00040000 0x00100000 0 287 * 2: env2 0x00040000 0x00140000 0 288 * 3: UBI 0x03e80000 0x00180000 0 289 * 4: boot 0x00e80000 0x00180000 0 290 * 5: rootfs 0x01000000 0x01000000 0 291 * 292 */ 293 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 294 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 295 "1m(u-boot)," \ 296 "256k(env1)," \ 297 "256k(env2)," \ 298 "14848k(boot)," \ 299 "16m(rootfs)," \ 300 "-@1536k(UBI)\0" 301 #endif 302 303 /* UBI and UBIFS support */ 304 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 305 #define CONFIG_CMD_UBI 306 #define CONFIG_CMD_UBIFS 307 #define CONFIG_RBTREE 308 #define CONFIG_LZO 309 #endif 310 311 /* 312 * SPL 313 * 314 * SRAM Memory layout: 315 * 316 * 0xFFFF_0000 ...... Start of SRAM 317 * 0xFFFF_xxxx ...... Top of stack (grows down) 318 * 0xFFFF_yyyy ...... Malloc area 319 * 0xFFFF_zzzz ...... Global Data 320 * 0xFFFF_FF00 ...... End of SRAM 321 */ 322 #define CONFIG_SPL_FRAMEWORK 323 #define CONFIG_SPL_RAM_DEVICE 324 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 325 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 326 327 #define CONFIG_SPL_LIBCOMMON_SUPPORT 328 #define CONFIG_SPL_LIBGENERIC_SUPPORT 329 #define CONFIG_SPL_WATCHDOG_SUPPORT 330 #define CONFIG_SPL_SERIAL_SUPPORT 331 #ifdef CONFIG_DM_MMC 332 #define CONFIG_SPL_MMC_SUPPORT 333 #endif 334 #ifdef CONFIG_DM_SPI 335 #define CONFIG_SPL_SPI_SUPPORT 336 #endif 337 #ifdef CONFIG_SPL_NAND_DENALI 338 #define CONFIG_SPL_NAND_SUPPORT 339 #endif 340 341 /* SPL SDMMC boot support */ 342 #ifdef CONFIG_SPL_MMC_SUPPORT 343 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 344 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 345 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 346 #define CONFIG_SPL_LIBDISK_SUPPORT 347 #else 348 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 349 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ 350 #define CONFIG_SPL_LIBDISK_SUPPORT 351 #endif 352 #endif 353 354 /* SPL QSPI boot support */ 355 #ifdef CONFIG_SPL_SPI_SUPPORT 356 #define CONFIG_SPL_SPI_FLASH_SUPPORT 357 #define CONFIG_SPL_SPI_LOAD 358 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 359 #endif 360 361 /* SPL NAND boot support */ 362 #ifdef CONFIG_SPL_NAND_SUPPORT 363 #define CONFIG_SYS_NAND_USE_FLASH_BBT 364 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 365 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 366 #endif 367 368 /* 369 * Stack setup 370 */ 371 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 372 373 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 374