1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22 /* add target to build it automatically upon "make" */ 23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25 /* 26 * Memory configurations 27 */ 28 #define CONFIG_NR_DRAM_BANKS 1 29 #define PHYS_SDRAM_1 0x0 30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39 #endif 40 #define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 47 #define CONFIG_SYS_TEXT_BASE 0x08000040 48 #else 49 #define CONFIG_SYS_TEXT_BASE 0x01000040 50 #endif 51 52 /* 53 * U-Boot general configurations 54 */ 55 #define CONFIG_SYS_LONGHELP 56 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 57 /* Print buffer size */ 58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 60 /* Boot argument buffer size */ 61 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 62 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 63 64 #ifndef CONFIG_SYS_HOSTNAME 65 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 66 #endif 67 68 #define CONFIG_CMD_PXE 69 #define CONFIG_MENU 70 71 /* 72 * Cache 73 */ 74 #define CONFIG_SYS_L2_PL310 75 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 76 77 /* 78 * EPCS/EPCQx1 Serial Flash Controller 79 */ 80 #ifdef CONFIG_ALTERA_SPI 81 #define CONFIG_SF_DEFAULT_SPEED 30000000 82 /* 83 * The base address is configurable in QSys, each board must specify the 84 * base address based on it's particular FPGA configuration. Please note 85 * that the address here is incremented by 0x400 from the Base address 86 * selected in QSys, since the SPI registers are at offset +0x400. 87 * #define CONFIG_SYS_SPI_BASE 0xff240400 88 */ 89 #endif 90 91 /* 92 * Ethernet on SoC (EMAC) 93 */ 94 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 95 #define CONFIG_DW_ALTDESCRIPTOR 96 #define CONFIG_MII 97 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 98 #endif 99 100 /* 101 * FPGA Driver 102 */ 103 #ifdef CONFIG_CMD_FPGA 104 #define CONFIG_FPGA_COUNT 1 105 #endif 106 107 /* 108 * L4 OSC1 Timer 0 109 */ 110 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 111 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 112 #define CONFIG_SYS_TIMER_COUNTS_DOWN 113 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 114 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 115 #define CONFIG_SYS_TIMER_RATE 2400000 116 #else 117 #define CONFIG_SYS_TIMER_RATE 25000000 118 #endif 119 120 /* 121 * L4 Watchdog 122 */ 123 #ifdef CONFIG_HW_WATCHDOG 124 #define CONFIG_DESIGNWARE_WATCHDOG 125 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 126 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 127 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 128 #endif 129 130 /* 131 * MMC Driver 132 */ 133 #ifdef CONFIG_CMD_MMC 134 #define CONFIG_BOUNCE_BUFFER 135 /* FIXME */ 136 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 137 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 138 #endif 139 140 /* 141 * NAND Support 142 */ 143 #ifdef CONFIG_NAND_DENALI 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 145 #define CONFIG_SYS_NAND_ONFI_DETECTION 146 #define CONFIG_NAND_DENALI_ECC_SIZE 512 147 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 148 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 149 #endif 150 151 /* 152 * I2C support 153 */ 154 #define CONFIG_SYS_I2C 155 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 156 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 157 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 158 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 159 /* Using standard mode which the speed up to 100Kb/s */ 160 #define CONFIG_SYS_I2C_SPEED 100000 161 #define CONFIG_SYS_I2C_SPEED1 100000 162 #define CONFIG_SYS_I2C_SPEED2 100000 163 #define CONFIG_SYS_I2C_SPEED3 100000 164 /* Address of device when used as slave */ 165 #define CONFIG_SYS_I2C_SLAVE 0x02 166 #define CONFIG_SYS_I2C_SLAVE1 0x02 167 #define CONFIG_SYS_I2C_SLAVE2 0x02 168 #define CONFIG_SYS_I2C_SLAVE3 0x02 169 #ifndef __ASSEMBLY__ 170 /* Clock supplied to I2C controller in unit of MHz */ 171 unsigned int cm_get_l4_sp_clk_hz(void); 172 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 173 #endif 174 175 /* 176 * QSPI support 177 */ 178 /* Enable multiple SPI NOR flash manufacturers */ 179 #ifndef CONFIG_SPL_BUILD 180 #define CONFIG_SPI_FLASH_MTD 181 #define CONFIG_MTD_DEVICE 182 #define CONFIG_MTD_PARTITIONS 183 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 184 #endif 185 /* QSPI reference clock */ 186 #ifndef __ASSEMBLY__ 187 unsigned int cm_get_qspi_controller_clk_hz(void); 188 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 189 #endif 190 #define CONFIG_CQSPI_DECODER 0 191 #define CONFIG_BOUNCE_BUFFER 192 193 /* 194 * Designware SPI support 195 */ 196 197 /* 198 * Serial Driver 199 */ 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE -4 202 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 203 #define CONFIG_SYS_NS16550_CLK 1000000 204 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 205 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 206 #define CONFIG_SYS_NS16550_CLK 100000000 207 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 208 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 209 #define CONFIG_SYS_NS16550_CLK 50000000 210 #endif 211 #define CONFIG_CONS_INDEX 1 212 213 /* 214 * USB 215 */ 216 217 /* 218 * USB Gadget (DFU, UMS) 219 */ 220 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 221 #define CONFIG_USB_FUNCTION_MASS_STORAGE 222 223 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 224 #define DFU_DEFAULT_POLL_TIMEOUT 300 225 226 /* USB IDs */ 227 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 228 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 229 #endif 230 231 /* 232 * U-Boot environment 233 */ 234 #if !defined(CONFIG_ENV_SIZE) 235 #define CONFIG_ENV_SIZE (8 * 1024) 236 #endif 237 238 /* Environment for SDMMC boot */ 239 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 240 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 241 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 242 #endif 243 244 /* Environment for QSPI boot */ 245 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 246 #define CONFIG_ENV_OFFSET 0x00100000 247 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 248 #endif 249 250 /* 251 * mtd partitioning for serial NOR flash 252 * 253 * device nor0 <ff705000.spi.0>, # parts = 6 254 * #: name size offset mask_flags 255 * 0: u-boot 0x00100000 0x00000000 0 256 * 1: env1 0x00040000 0x00100000 0 257 * 2: env2 0x00040000 0x00140000 0 258 * 3: UBI 0x03e80000 0x00180000 0 259 * 4: boot 0x00e80000 0x00180000 0 260 * 5: rootfs 0x01000000 0x01000000 0 261 * 262 */ 263 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 264 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 265 "1m(u-boot)," \ 266 "256k(env1)," \ 267 "256k(env2)," \ 268 "14848k(boot)," \ 269 "16m(rootfs)," \ 270 "-@1536k(UBI)\0" 271 #endif 272 273 /* 274 * SPL 275 * 276 * SRAM Memory layout: 277 * 278 * 0xFFFF_0000 ...... Start of SRAM 279 * 0xFFFF_xxxx ...... Top of stack (grows down) 280 * 0xFFFF_yyyy ...... Malloc area 281 * 0xFFFF_zzzz ...... Global Data 282 * 0xFFFF_FF00 ...... End of SRAM 283 */ 284 #define CONFIG_SPL_FRAMEWORK 285 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 286 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 287 288 /* SPL SDMMC boot support */ 289 #ifdef CONFIG_SPL_MMC_SUPPORT 290 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 291 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 292 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 293 #endif 294 #else 295 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 296 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 297 #endif 298 #endif 299 300 /* SPL QSPI boot support */ 301 #ifdef CONFIG_SPL_SPI_SUPPORT 302 #define CONFIG_SPL_SPI_LOAD 303 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 304 #endif 305 306 /* SPL NAND boot support */ 307 #ifdef CONFIG_SPL_NAND_SUPPORT 308 #define CONFIG_SYS_NAND_USE_FLASH_BBT 309 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 310 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 311 #endif 312 313 /* 314 * Stack setup 315 */ 316 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 317 318 /* Extra Environment */ 319 #ifndef CONFIG_SPL_BUILD 320 #include <config_distro_defaults.h> 321 322 #ifdef CONFIG_CMD_PXE 323 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 324 #else 325 #define BOOT_TARGET_DEVICES_PXE(func) 326 #endif 327 328 #ifdef CONFIG_CMD_MMC 329 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 330 #else 331 #define BOOT_TARGET_DEVICES_MMC(func) 332 #endif 333 334 #define BOOT_TARGET_DEVICES(func) \ 335 BOOT_TARGET_DEVICES_MMC(func) \ 336 BOOT_TARGET_DEVICES_PXE(func) \ 337 func(DHCP, dhcp, na) 338 339 #include <config_distro_bootcmd.h> 340 341 #ifndef CONFIG_EXTRA_ENV_SETTINGS 342 #define CONFIG_EXTRA_ENV_SETTINGS \ 343 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 344 "bootm_size=0xa000000\0" \ 345 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 346 "fdt_addr_r=0x02000000\0" \ 347 "scriptaddr=0x02100000\0" \ 348 "pxefile_addr_r=0x02200000\0" \ 349 "ramdisk_addr_r=0x02300000\0" \ 350 BOOTENV 351 352 #endif 353 #endif 354 355 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 356