1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 8 9 #define CONFIG_SYS_GENERIC_BOARD 10 11 /* Virtual target or real hardware */ 12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 13 14 #define CONFIG_ARMV7 15 #define CONFIG_SYS_THUMB_BUILD 16 17 #define CONFIG_SOCFPGA 18 19 /* 20 * High level configuration 21 */ 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 #define CONFIG_BOARD_EARLY_INIT_F 25 #define CONFIG_ARCH_EARLY_INIT_R 26 #define CONFIG_SYS_NO_FLASH 27 #define CONFIG_CLOCKS 28 29 #define CONFIG_FIT 30 #define CONFIG_OF_LIBFDT 31 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 32 33 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 34 35 /* 36 * Memory configurations 37 */ 38 #define CONFIG_NR_DRAM_BANKS 1 39 #define PHYS_SDRAM_1 0x0 40 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 41 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 42 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 43 44 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 45 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ 48 GENERATED_GBL_DATA_SIZE) 49 50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 52 #define CONFIG_SYS_TEXT_BASE 0x08000040 53 #else 54 #define CONFIG_SYS_TEXT_BASE 0x01000040 55 #endif 56 57 /* 58 * U-Boot general configurations 59 */ 60 #define CONFIG_SYS_LONGHELP 61 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 62 #define CONFIG_SYS_PBSIZE \ 63 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 64 /* Print buffer size */ 65 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 67 /* Boot argument buffer size */ 68 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 69 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 70 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 71 #define CONFIG_SYS_HUSH_PARSER 72 73 /* 74 * Cache 75 */ 76 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC 77 #define CONFIG_SYS_CACHELINE_SIZE 32 78 #define CONFIG_SYS_L2_PL310 79 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 80 81 /* 82 * EPCS/EPCQx1 Serial Flash Controller 83 */ 84 #ifdef CONFIG_ALTERA_SPI 85 #define CONFIG_CMD_SPI 86 #define CONFIG_CMD_SF 87 #define CONFIG_SF_DEFAULT_SPEED 30000000 88 #define CONFIG_SPI_FLASH 89 #define CONFIG_SPI_FLASH_STMICRO 90 #define CONFIG_SPI_FLASH_BAR 91 /* 92 * The base address is configurable in QSys, each board must specify the 93 * base address based on it's particular FPGA configuration. Please note 94 * that the address here is incremented by 0x400 from the Base address 95 * selected in QSys, since the SPI registers are at offset +0x400. 96 * #define CONFIG_SYS_SPI_BASE 0xff240400 97 */ 98 #endif 99 100 /* 101 * Ethernet on SoC (EMAC) 102 */ 103 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 104 #define CONFIG_DESIGNWARE_ETH 105 #define CONFIG_NET_MULTI 106 #define CONFIG_DW_ALTDESCRIPTOR 107 #define CONFIG_MII 108 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 109 #define CONFIG_PHYLIB 110 #define CONFIG_PHY_GIGE 111 #endif 112 113 /* 114 * FPGA Driver 115 */ 116 #ifdef CONFIG_CMD_FPGA 117 #define CONFIG_FPGA 118 #define CONFIG_FPGA_ALTERA 119 #define CONFIG_FPGA_SOCFPGA 120 #define CONFIG_FPGA_COUNT 1 121 #endif 122 123 /* 124 * L4 OSC1 Timer 0 125 */ 126 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 127 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 128 #define CONFIG_SYS_TIMER_COUNTS_DOWN 129 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 130 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 131 #define CONFIG_SYS_TIMER_RATE 2400000 132 #else 133 #define CONFIG_SYS_TIMER_RATE 25000000 134 #endif 135 136 /* 137 * L4 Watchdog 138 */ 139 #ifdef CONFIG_HW_WATCHDOG 140 #define CONFIG_DESIGNWARE_WATCHDOG 141 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 142 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 143 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 144 #endif 145 146 /* 147 * MMC Driver 148 */ 149 #ifdef CONFIG_CMD_MMC 150 #define CONFIG_MMC 151 #define CONFIG_BOUNCE_BUFFER 152 #define CONFIG_GENERIC_MMC 153 #define CONFIG_DWMMC 154 #define CONFIG_SOCFPGA_DWMMC 155 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 156 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 157 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 158 /* FIXME */ 159 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 160 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 161 #endif 162 163 /* 164 * I2C support 165 */ 166 #define CONFIG_SYS_I2C 167 #define CONFIG_SYS_I2C_DW 168 #define CONFIG_SYS_I2C_BUS_MAX 4 169 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 170 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 171 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 172 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 173 /* Using standard mode which the speed up to 100Kb/s */ 174 #define CONFIG_SYS_I2C_SPEED 100000 175 #define CONFIG_SYS_I2C_SPEED1 100000 176 #define CONFIG_SYS_I2C_SPEED2 100000 177 #define CONFIG_SYS_I2C_SPEED3 100000 178 /* Address of device when used as slave */ 179 #define CONFIG_SYS_I2C_SLAVE 0x02 180 #define CONFIG_SYS_I2C_SLAVE1 0x02 181 #define CONFIG_SYS_I2C_SLAVE2 0x02 182 #define CONFIG_SYS_I2C_SLAVE3 0x02 183 #ifndef __ASSEMBLY__ 184 /* Clock supplied to I2C controller in unit of MHz */ 185 unsigned int cm_get_l4_sp_clk_hz(void); 186 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 187 #endif 188 #define CONFIG_CMD_I2C 189 190 /* 191 * Serial Driver 192 */ 193 #define CONFIG_SYS_NS16550 194 #define CONFIG_SYS_NS16550_SERIAL 195 #define CONFIG_SYS_NS16550_REG_SIZE -4 196 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 197 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 198 #define CONFIG_SYS_NS16550_CLK 1000000 199 #else 200 #define CONFIG_SYS_NS16550_CLK 100000000 201 #endif 202 #define CONFIG_CONS_INDEX 1 203 #define CONFIG_BAUDRATE 115200 204 205 /* 206 * USB 207 */ 208 #ifdef CONFIG_CMD_USB 209 #define CONFIG_USB_DWC2 210 #define CONFIG_USB_STORAGE 211 /* 212 * NOTE: User must define either of the following to select which 213 * of the two USB controllers available on SoCFPGA to use. 214 * The DWC2 driver doesn't support multiple USB controllers. 215 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS 216 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS 217 */ 218 #endif 219 220 /* 221 * USB Gadget (DFU, UMS) 222 */ 223 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 224 #define CONFIG_USB_GADGET 225 #define CONFIG_USB_GADGET_S3C_UDC_OTG 226 #define CONFIG_USB_GADGET_DUALSPEED 227 #define CONFIG_USB_GADGET_VBUS_DRAW 2 228 229 /* USB Composite download gadget - g_dnl */ 230 #define CONFIG_USBDOWNLOAD_GADGET 231 #define CONFIG_USB_GADGET_MASS_STORAGE 232 233 #define CONFIG_DFU_FUNCTION 234 #define CONFIG_DFU_MMC 235 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 236 #define DFU_DEFAULT_POLL_TIMEOUT 300 237 238 /* USB IDs */ 239 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 240 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 241 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 242 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 243 #ifndef CONFIG_G_DNL_MANUFACTURER 244 #define CONFIG_G_DNL_MANUFACTURER "Altera" 245 #endif 246 #endif 247 248 /* 249 * U-Boot environment 250 */ 251 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 252 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 253 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 254 #define CONFIG_ENV_IS_NOWHERE 255 #define CONFIG_ENV_SIZE 4096 256 257 /* 258 * SPL 259 * 260 * SRAM Memory layout: 261 * 262 * 0xFFFF_0000 ...... Start of SRAM 263 * 0xFFFF_xxxx ...... Top of stack (grows down) 264 * 0xFFFF_yyyy ...... Malloc area 265 * 0xFFFF_zzzz ...... Global Data 266 * 0xFFFF_FF00 ...... End of SRAM 267 */ 268 #define CONFIG_SPL_FRAMEWORK 269 #define CONFIG_SPL_BOARD_INIT 270 #define CONFIG_SPL_RAM_DEVICE 271 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 272 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR 273 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) 274 275 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ 276 #define CONFIG_CRC32_VERIFY 277 278 /* Linker script for SPL */ 279 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" 280 281 #define CONFIG_SPL_LIBCOMMON_SUPPORT 282 #define CONFIG_SPL_LIBGENERIC_SUPPORT 283 #define CONFIG_SPL_WATCHDOG_SUPPORT 284 #define CONFIG_SPL_SERIAL_SUPPORT 285 286 #ifdef CONFIG_SPL_BUILD 287 #undef CONFIG_PARTITIONS 288 #endif 289 290 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ 291