1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 8 9 #define CONFIG_SYS_GENERIC_BOARD 10 11 /* Virtual target or real hardware */ 12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 13 14 #define CONFIG_SYS_THUMB_BUILD 15 16 #define CONFIG_SOCFPGA 17 18 /* 19 * High level configuration 20 */ 21 #define CONFIG_DISPLAY_CPUINFO 22 #define CONFIG_DISPLAY_BOARDINFO_LATE 23 #define CONFIG_ARCH_EARLY_INIT_R 24 #define CONFIG_SYS_NO_FLASH 25 #define CONFIG_CLOCKS 26 27 #define CONFIG_FIT 28 #define CONFIG_OF_LIBFDT 29 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* 34 * Memory configurations 35 */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define PHYS_SDRAM_1 0x0 38 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 39 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 40 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 41 42 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 43 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) 44 #define CONFIG_SYS_INIT_SP_ADDR \ 45 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ 46 GENERATED_GBL_DATA_SIZE) 47 48 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 49 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 50 #define CONFIG_SYS_TEXT_BASE 0x08000040 51 #else 52 #define CONFIG_SYS_TEXT_BASE 0x01000040 53 #endif 54 55 /* 56 * U-Boot general configurations 57 */ 58 #define CONFIG_SYS_LONGHELP 59 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 60 #define CONFIG_SYS_PBSIZE \ 61 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 62 /* Print buffer size */ 63 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 65 /* Boot argument buffer size */ 66 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 67 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 68 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 69 #define CONFIG_SYS_HUSH_PARSER 70 71 /* 72 * Cache 73 */ 74 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC 75 #define CONFIG_SYS_CACHELINE_SIZE 32 76 #define CONFIG_SYS_L2_PL310 77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 78 79 /* 80 * EPCS/EPCQx1 Serial Flash Controller 81 */ 82 #ifdef CONFIG_ALTERA_SPI 83 #define CONFIG_CMD_SPI 84 #define CONFIG_CMD_SF 85 #define CONFIG_SF_DEFAULT_SPEED 30000000 86 #define CONFIG_SPI_FLASH 87 #define CONFIG_SPI_FLASH_STMICRO 88 #define CONFIG_SPI_FLASH_BAR 89 /* 90 * The base address is configurable in QSys, each board must specify the 91 * base address based on it's particular FPGA configuration. Please note 92 * that the address here is incremented by 0x400 from the Base address 93 * selected in QSys, since the SPI registers are at offset +0x400. 94 * #define CONFIG_SYS_SPI_BASE 0xff240400 95 */ 96 #endif 97 98 /* 99 * Ethernet on SoC (EMAC) 100 */ 101 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 102 #define CONFIG_DESIGNWARE_ETH 103 #define CONFIG_NET_MULTI 104 #define CONFIG_DW_ALTDESCRIPTOR 105 #define CONFIG_MII 106 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 107 #define CONFIG_PHYLIB 108 #define CONFIG_PHY_GIGE 109 #endif 110 111 /* 112 * FPGA Driver 113 */ 114 #ifdef CONFIG_CMD_FPGA 115 #define CONFIG_FPGA 116 #define CONFIG_FPGA_ALTERA 117 #define CONFIG_FPGA_SOCFPGA 118 #define CONFIG_FPGA_COUNT 1 119 #endif 120 121 /* 122 * L4 OSC1 Timer 0 123 */ 124 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 125 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 126 #define CONFIG_SYS_TIMER_COUNTS_DOWN 127 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 128 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 129 #define CONFIG_SYS_TIMER_RATE 2400000 130 #else 131 #define CONFIG_SYS_TIMER_RATE 25000000 132 #endif 133 134 /* 135 * L4 Watchdog 136 */ 137 #ifdef CONFIG_HW_WATCHDOG 138 #define CONFIG_DESIGNWARE_WATCHDOG 139 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 140 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 141 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 142 #endif 143 144 /* 145 * MMC Driver 146 */ 147 #ifdef CONFIG_CMD_MMC 148 #define CONFIG_MMC 149 #define CONFIG_BOUNCE_BUFFER 150 #define CONFIG_GENERIC_MMC 151 #define CONFIG_DWMMC 152 #define CONFIG_SOCFPGA_DWMMC 153 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 154 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 155 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 156 /* FIXME */ 157 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 158 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 159 #endif 160 161 /* 162 * I2C support 163 */ 164 #define CONFIG_SYS_I2C 165 #define CONFIG_SYS_I2C_DW 166 #define CONFIG_SYS_I2C_BUS_MAX 4 167 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 168 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 169 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 170 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 171 /* Using standard mode which the speed up to 100Kb/s */ 172 #define CONFIG_SYS_I2C_SPEED 100000 173 #define CONFIG_SYS_I2C_SPEED1 100000 174 #define CONFIG_SYS_I2C_SPEED2 100000 175 #define CONFIG_SYS_I2C_SPEED3 100000 176 /* Address of device when used as slave */ 177 #define CONFIG_SYS_I2C_SLAVE 0x02 178 #define CONFIG_SYS_I2C_SLAVE1 0x02 179 #define CONFIG_SYS_I2C_SLAVE2 0x02 180 #define CONFIG_SYS_I2C_SLAVE3 0x02 181 #ifndef __ASSEMBLY__ 182 /* Clock supplied to I2C controller in unit of MHz */ 183 unsigned int cm_get_l4_sp_clk_hz(void); 184 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 185 #endif 186 #define CONFIG_CMD_I2C 187 188 /* 189 * QSPI support 190 */ 191 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ 192 #define CONFIG_CADENCE_QSPI 193 /* Enable multiple SPI NOR flash manufacturers */ 194 #define CONFIG_SPI_FLASH /* SPI flash subsystem */ 195 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ 196 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ 197 #define CONFIG_SPI_FLASH_MTD 198 /* QSPI reference clock */ 199 #ifndef __ASSEMBLY__ 200 unsigned int cm_get_qspi_controller_clk_hz(void); 201 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 202 #endif 203 #define CONFIG_CQSPI_DECODER 0 204 #define CONFIG_CMD_SF 205 #endif 206 207 #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ 208 #define CONFIG_DESIGNWARE_SPI 209 #define CONFIG_CMD_SPI 210 #endif 211 212 /* 213 * Serial Driver 214 */ 215 #define CONFIG_SYS_NS16550 216 #define CONFIG_SYS_NS16550_SERIAL 217 #define CONFIG_SYS_NS16550_REG_SIZE -4 218 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 219 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 220 #define CONFIG_SYS_NS16550_CLK 1000000 221 #else 222 #define CONFIG_SYS_NS16550_CLK 100000000 223 #endif 224 #define CONFIG_CONS_INDEX 1 225 #define CONFIG_BAUDRATE 115200 226 227 /* 228 * USB 229 */ 230 #ifdef CONFIG_CMD_USB 231 #define CONFIG_USB_DWC2 232 #define CONFIG_USB_STORAGE 233 /* 234 * NOTE: User must define either of the following to select which 235 * of the two USB controllers available on SoCFPGA to use. 236 * The DWC2 driver doesn't support multiple USB controllers. 237 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS 238 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS 239 */ 240 #endif 241 242 /* 243 * USB Gadget (DFU, UMS) 244 */ 245 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 246 #define CONFIG_USB_GADGET 247 #define CONFIG_USB_GADGET_S3C_UDC_OTG 248 #define CONFIG_USB_GADGET_DUALSPEED 249 #define CONFIG_USB_GADGET_VBUS_DRAW 2 250 251 /* USB Composite download gadget - g_dnl */ 252 #define CONFIG_USBDOWNLOAD_GADGET 253 #define CONFIG_USB_GADGET_MASS_STORAGE 254 255 #define CONFIG_DFU_FUNCTION 256 #define CONFIG_DFU_MMC 257 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 258 #define DFU_DEFAULT_POLL_TIMEOUT 300 259 260 /* USB IDs */ 261 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 262 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 263 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 264 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 265 #ifndef CONFIG_G_DNL_MANUFACTURER 266 #define CONFIG_G_DNL_MANUFACTURER "Altera" 267 #endif 268 #endif 269 270 /* 271 * U-Boot environment 272 */ 273 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 274 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 275 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 276 #define CONFIG_ENV_IS_NOWHERE 277 #define CONFIG_ENV_SIZE 4096 278 279 /* 280 * SPL 281 * 282 * SRAM Memory layout: 283 * 284 * 0xFFFF_0000 ...... Start of SRAM 285 * 0xFFFF_xxxx ...... Top of stack (grows down) 286 * 0xFFFF_yyyy ...... Malloc area 287 * 0xFFFF_zzzz ...... Global Data 288 * 0xFFFF_FF00 ...... End of SRAM 289 */ 290 #define CONFIG_SPL_FRAMEWORK 291 #define CONFIG_SPL_BOARD_INIT 292 #define CONFIG_SPL_RAM_DEVICE 293 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 294 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR 295 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) 296 297 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ 298 #define CONFIG_CRC32_VERIFY 299 300 /* Linker script for SPL */ 301 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" 302 303 #define CONFIG_SPL_LIBCOMMON_SUPPORT 304 #define CONFIG_SPL_LIBGENERIC_SUPPORT 305 #define CONFIG_SPL_WATCHDOG_SUPPORT 306 #define CONFIG_SPL_SERIAL_SUPPORT 307 308 #ifdef CONFIG_SPL_BUILD 309 #undef CONFIG_PARTITIONS 310 #endif 311 312 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ 313