1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 10 /* Virtual target or real hardware */ 11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 12 13 #define CONFIG_SYS_THUMB_BUILD 14 15 /* 16 * High level configuration 17 */ 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO_LATE 20 #define CONFIG_ARCH_MISC_INIT 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_CRC32_VERIFY 26 27 #define CONFIG_FIT 28 #define CONFIG_OF_LIBFDT 29 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* add target to build it automatically upon "make" */ 34 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 35 36 /* 37 * Memory configurations 38 */ 39 #define CONFIG_NR_DRAM_BANKS 1 40 #define PHYS_SDRAM_1 0x0 41 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 42 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 43 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 44 45 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 46 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 47 #define CONFIG_SYS_INIT_SP_OFFSET \ 48 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 49 #define CONFIG_SYS_INIT_SP_ADDR \ 50 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 51 52 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 53 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 54 #define CONFIG_SYS_TEXT_BASE 0x08000040 55 #else 56 #define CONFIG_SYS_TEXT_BASE 0x01000040 57 #endif 58 59 /* 60 * U-Boot general configurations 61 */ 62 #define CONFIG_SYS_LONGHELP 63 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 64 #define CONFIG_SYS_PBSIZE \ 65 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 66 /* Print buffer size */ 67 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 68 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 69 /* Boot argument buffer size */ 70 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 71 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 72 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 73 #define CONFIG_SYS_HUSH_PARSER 74 75 #ifndef CONFIG_SYS_HOSTNAME 76 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 77 #endif 78 79 /* 80 * Cache 81 */ 82 #define CONFIG_SYS_CACHELINE_SIZE 32 83 #define CONFIG_SYS_L2_PL310 84 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 85 86 /* 87 * SDRAM controller 88 */ 89 #define CONFIG_ALTERA_SDRAM 90 91 /* 92 * EPCS/EPCQx1 Serial Flash Controller 93 */ 94 #ifdef CONFIG_ALTERA_SPI 95 #define CONFIG_CMD_SPI 96 #define CONFIG_CMD_SF 97 #define CONFIG_SF_DEFAULT_SPEED 30000000 98 #define CONFIG_SPI_FLASH_BAR 99 /* 100 * The base address is configurable in QSys, each board must specify the 101 * base address based on it's particular FPGA configuration. Please note 102 * that the address here is incremented by 0x400 from the Base address 103 * selected in QSys, since the SPI registers are at offset +0x400. 104 * #define CONFIG_SYS_SPI_BASE 0xff240400 105 */ 106 #endif 107 108 /* 109 * Ethernet on SoC (EMAC) 110 */ 111 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 112 #define CONFIG_DW_ALTDESCRIPTOR 113 #define CONFIG_MII 114 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 115 #define CONFIG_PHY_GIGE 116 #endif 117 118 /* 119 * FPGA Driver 120 */ 121 #ifdef CONFIG_CMD_FPGA 122 #define CONFIG_FPGA 123 #define CONFIG_FPGA_ALTERA 124 #define CONFIG_FPGA_SOCFPGA 125 #define CONFIG_FPGA_COUNT 1 126 #endif 127 128 /* 129 * L4 OSC1 Timer 0 130 */ 131 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 132 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 133 #define CONFIG_SYS_TIMER_COUNTS_DOWN 134 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 135 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 136 #define CONFIG_SYS_TIMER_RATE 2400000 137 #else 138 #define CONFIG_SYS_TIMER_RATE 25000000 139 #endif 140 141 /* 142 * L4 Watchdog 143 */ 144 #ifdef CONFIG_HW_WATCHDOG 145 #define CONFIG_DESIGNWARE_WATCHDOG 146 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 147 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 148 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 149 #endif 150 151 /* 152 * MMC Driver 153 */ 154 #ifdef CONFIG_CMD_MMC 155 #define CONFIG_MMC 156 #define CONFIG_BOUNCE_BUFFER 157 #define CONFIG_GENERIC_MMC 158 #define CONFIG_DWMMC 159 #define CONFIG_SOCFPGA_DWMMC 160 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 161 /* FIXME */ 162 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 163 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 164 #endif 165 166 /* 167 * NAND Support 168 */ 169 #ifdef CONFIG_NAND_DENALI 170 #define CONFIG_SYS_MAX_NAND_DEVICE 1 171 #define CONFIG_SYS_NAND_MAX_CHIPS 1 172 #define CONFIG_SYS_NAND_ONFI_DETECTION 173 #define CONFIG_NAND_DENALI_ECC_SIZE 512 174 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 175 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 176 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 177 #endif 178 179 /* 180 * I2C support 181 */ 182 #define CONFIG_SYS_I2C 183 #define CONFIG_SYS_I2C_DW 184 #define CONFIG_SYS_I2C_BUS_MAX 4 185 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 186 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 187 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 188 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 189 /* Using standard mode which the speed up to 100Kb/s */ 190 #define CONFIG_SYS_I2C_SPEED 100000 191 #define CONFIG_SYS_I2C_SPEED1 100000 192 #define CONFIG_SYS_I2C_SPEED2 100000 193 #define CONFIG_SYS_I2C_SPEED3 100000 194 /* Address of device when used as slave */ 195 #define CONFIG_SYS_I2C_SLAVE 0x02 196 #define CONFIG_SYS_I2C_SLAVE1 0x02 197 #define CONFIG_SYS_I2C_SLAVE2 0x02 198 #define CONFIG_SYS_I2C_SLAVE3 0x02 199 #ifndef __ASSEMBLY__ 200 /* Clock supplied to I2C controller in unit of MHz */ 201 unsigned int cm_get_l4_sp_clk_hz(void); 202 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 203 #endif 204 #define CONFIG_CMD_I2C 205 206 /* 207 * QSPI support 208 */ 209 /* Enable multiple SPI NOR flash manufacturers */ 210 #ifndef CONFIG_SPL_BUILD 211 #define CONFIG_SPI_FLASH_MTD 212 #define CONFIG_CMD_MTDPARTS 213 #define CONFIG_MTD_DEVICE 214 #define CONFIG_MTD_PARTITIONS 215 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 216 #endif 217 /* QSPI reference clock */ 218 #ifndef __ASSEMBLY__ 219 unsigned int cm_get_qspi_controller_clk_hz(void); 220 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 221 #endif 222 #define CONFIG_CQSPI_DECODER 0 223 #define CONFIG_CMD_SF 224 #define CONFIG_SPI_FLASH_BAR 225 226 /* 227 * Designware SPI support 228 */ 229 #define CONFIG_CMD_SPI 230 231 /* 232 * Serial Driver 233 */ 234 #define CONFIG_SYS_NS16550_SERIAL 235 #define CONFIG_SYS_NS16550_REG_SIZE -4 236 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 237 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 238 #define CONFIG_SYS_NS16550_CLK 1000000 239 #else 240 #define CONFIG_SYS_NS16550_CLK 100000000 241 #endif 242 #define CONFIG_CONS_INDEX 1 243 #define CONFIG_BAUDRATE 115200 244 245 /* 246 * USB 247 */ 248 #ifdef CONFIG_CMD_USB 249 #define CONFIG_USB_DWC2 250 #define CONFIG_USB_STORAGE 251 #endif 252 253 /* 254 * USB Gadget (DFU, UMS) 255 */ 256 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 257 #define CONFIG_USB_GADGET 258 #define CONFIG_USB_GADGET_DWC2_OTG 259 #define CONFIG_USB_GADGET_DUALSPEED 260 #define CONFIG_USB_GADGET_VBUS_DRAW 2 261 262 /* USB Composite download gadget - g_dnl */ 263 #define CONFIG_USB_GADGET_DOWNLOAD 264 #define CONFIG_USB_FUNCTION_MASS_STORAGE 265 266 #define CONFIG_USB_FUNCTION_DFU 267 #ifdef CONFIG_DM_MMC 268 #define CONFIG_DFU_MMC 269 #endif 270 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 271 #define DFU_DEFAULT_POLL_TIMEOUT 300 272 273 /* USB IDs */ 274 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 275 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 276 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 277 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 278 #ifndef CONFIG_G_DNL_MANUFACTURER 279 #define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR 280 #endif 281 #endif 282 283 /* 284 * U-Boot environment 285 */ 286 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 287 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 288 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 289 #define CONFIG_ENV_SIZE 4096 290 291 /* Environment for SDMMC boot */ 292 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 293 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 294 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 295 #endif 296 297 /* 298 * mtd partitioning for serial NOR flash 299 * 300 * device nor0 <ff705000.spi.0>, # parts = 6 301 * #: name size offset mask_flags 302 * 0: u-boot 0x00100000 0x00000000 0 303 * 1: env1 0x00040000 0x00100000 0 304 * 2: env2 0x00040000 0x00140000 0 305 * 3: UBI 0x03e80000 0x00180000 0 306 * 4: boot 0x00e80000 0x00180000 0 307 * 5: rootfs 0x01000000 0x01000000 0 308 * 309 */ 310 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 311 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 312 "1m(u-boot)," \ 313 "256k(env1)," \ 314 "256k(env2)," \ 315 "14848k(boot)," \ 316 "16m(rootfs)," \ 317 "-@1536k(UBI)\0" 318 #endif 319 320 /* UBI and UBIFS support */ 321 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 322 #define CONFIG_CMD_UBI 323 #define CONFIG_CMD_UBIFS 324 #define CONFIG_RBTREE 325 #define CONFIG_LZO 326 #endif 327 328 /* 329 * SPL 330 * 331 * SRAM Memory layout: 332 * 333 * 0xFFFF_0000 ...... Start of SRAM 334 * 0xFFFF_xxxx ...... Top of stack (grows down) 335 * 0xFFFF_yyyy ...... Malloc area 336 * 0xFFFF_zzzz ...... Global Data 337 * 0xFFFF_FF00 ...... End of SRAM 338 */ 339 #define CONFIG_SPL_FRAMEWORK 340 #define CONFIG_SPL_RAM_DEVICE 341 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 342 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 343 #ifdef CONFIG_SPL_BUILD 344 #define CONFIG_SYS_MALLOC_SIMPLE 345 #endif 346 347 #define CONFIG_SPL_LIBCOMMON_SUPPORT 348 #define CONFIG_SPL_LIBGENERIC_SUPPORT 349 #define CONFIG_SPL_WATCHDOG_SUPPORT 350 #define CONFIG_SPL_SERIAL_SUPPORT 351 #ifdef CONFIG_DM_MMC 352 #define CONFIG_SPL_MMC_SUPPORT 353 #endif 354 #ifdef CONFIG_DM_SPI 355 #define CONFIG_SPL_SPI_SUPPORT 356 #endif 357 #ifdef CONFIG_SPL_NAND_DENALI 358 #define CONFIG_SPL_NAND_SUPPORT 359 #endif 360 361 /* SPL SDMMC boot support */ 362 #ifdef CONFIG_SPL_MMC_SUPPORT 363 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 364 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 365 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 366 #define CONFIG_SPL_LIBDISK_SUPPORT 367 #else 368 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 369 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 370 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 371 #endif 372 #endif 373 374 /* SPL QSPI boot support */ 375 #ifdef CONFIG_SPL_SPI_SUPPORT 376 #define CONFIG_SPL_SPI_FLASH_SUPPORT 377 #define CONFIG_SPL_SPI_LOAD 378 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 379 #endif 380 381 /* SPL NAND boot support */ 382 #ifdef CONFIG_SPL_NAND_SUPPORT 383 #define CONFIG_SYS_NAND_USE_FLASH_BBT 384 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 385 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 386 #endif 387 388 /* 389 * Stack setup 390 */ 391 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 392 393 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 394