1 /*
2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
7 #define __CONFIG_SOCFPGA_COMMON_H__
8 
9 /* Virtual target or real hardware */
10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
11 
12 /*
13  * High level configuration
14  */
15 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 #define CONFIG_CLOCKS
17 
18 #define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
19 
20 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
21 
22 /* add target to build it automatically upon "make" */
23 #define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"
24 
25 /*
26  * Memory configurations
27  */
28 #define CONFIG_NR_DRAM_BANKS		1
29 #define PHYS_SDRAM_1			0x0
30 #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
31 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
32 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
34 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
35 #define CONFIG_SYS_INIT_RAM_SIZE	0x10000
36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
37 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
38 #define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
39 #endif
40 #define CONFIG_SYS_INIT_SP_OFFSET		\
41 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
42 #define CONFIG_SYS_INIT_SP_ADDR			\
43 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
44 
45 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
47 #define CONFIG_SYS_TEXT_BASE		0x08000040
48 #else
49 #define CONFIG_SYS_TEXT_BASE		0x01000040
50 #endif
51 
52 /*
53  * U-Boot general configurations
54  */
55 #define CONFIG_SYS_LONGHELP
56 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
57 						/* Print buffer size */
58 #define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
59 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
60 						/* Boot argument buffer size */
61 #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
62 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
63 
64 #ifndef CONFIG_SYS_HOSTNAME
65 #define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
66 #endif
67 
68 #define CONFIG_CMD_PXE
69 #define CONFIG_MENU
70 
71 /*
72  * Cache
73  */
74 #define CONFIG_SYS_L2_PL310
75 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
76 
77 /*
78  * EPCS/EPCQx1 Serial Flash Controller
79  */
80 #ifdef CONFIG_ALTERA_SPI
81 #define CONFIG_SF_DEFAULT_SPEED		30000000
82 /*
83  * The base address is configurable in QSys, each board must specify the
84  * base address based on it's particular FPGA configuration. Please note
85  * that the address here is incremented by  0x400  from the Base address
86  * selected in QSys, since the SPI registers are at offset +0x400.
87  * #define CONFIG_SYS_SPI_BASE		0xff240400
88  */
89 #endif
90 
91 /*
92  * Ethernet on SoC (EMAC)
93  */
94 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
95 #define CONFIG_DW_ALTDESCRIPTOR
96 #define CONFIG_MII
97 #endif
98 
99 /*
100  * FPGA Driver
101  */
102 #ifdef CONFIG_CMD_FPGA
103 #define CONFIG_FPGA_COUNT		1
104 #endif
105 
106 /*
107  * L4 OSC1 Timer 0
108  */
109 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
110 #define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
111 #define CONFIG_SYS_TIMER_COUNTS_DOWN
112 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
113 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
114 #define CONFIG_SYS_TIMER_RATE		2400000
115 #else
116 #define CONFIG_SYS_TIMER_RATE		25000000
117 #endif
118 
119 /*
120  * L4 Watchdog
121  */
122 #ifdef CONFIG_HW_WATCHDOG
123 #define CONFIG_DESIGNWARE_WATCHDOG
124 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
125 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
126 #define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
127 #endif
128 
129 /*
130  * MMC Driver
131  */
132 #ifdef CONFIG_CMD_MMC
133 #define CONFIG_BOUNCE_BUFFER
134 /* FIXME */
135 /* using smaller max blk cnt to avoid flooding the limited stack we have */
136 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
137 #endif
138 
139 /*
140  * NAND Support
141  */
142 #ifdef CONFIG_NAND_DENALI
143 #define CONFIG_SYS_MAX_NAND_DEVICE	1
144 #define CONFIG_SYS_NAND_ONFI_DETECTION
145 #define CONFIG_NAND_DENALI_ECC_SIZE	512
146 #define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
147 #define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
148 #endif
149 
150 /*
151  * I2C support
152  */
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
155 #define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
156 #define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
157 #define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
158 /* Using standard mode which the speed up to 100Kb/s */
159 #define CONFIG_SYS_I2C_SPEED		100000
160 #define CONFIG_SYS_I2C_SPEED1		100000
161 #define CONFIG_SYS_I2C_SPEED2		100000
162 #define CONFIG_SYS_I2C_SPEED3		100000
163 /* Address of device when used as slave */
164 #define CONFIG_SYS_I2C_SLAVE		0x02
165 #define CONFIG_SYS_I2C_SLAVE1		0x02
166 #define CONFIG_SYS_I2C_SLAVE2		0x02
167 #define CONFIG_SYS_I2C_SLAVE3		0x02
168 #ifndef __ASSEMBLY__
169 /* Clock supplied to I2C controller in unit of MHz */
170 unsigned int cm_get_l4_sp_clk_hz(void);
171 #define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
172 #endif
173 
174 /*
175  * QSPI support
176  */
177 /* Enable multiple SPI NOR flash manufacturers */
178 #ifndef CONFIG_SPL_BUILD
179 #define CONFIG_SPI_FLASH_MTD
180 #define CONFIG_MTD_DEVICE
181 #define CONFIG_MTD_PARTITIONS
182 #endif
183 /* QSPI reference clock */
184 #ifndef __ASSEMBLY__
185 unsigned int cm_get_qspi_controller_clk_hz(void);
186 #define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
187 #endif
188 #define CONFIG_CQSPI_DECODER		0
189 #define CONFIG_BOUNCE_BUFFER
190 
191 /*
192  * Designware SPI support
193  */
194 
195 /*
196  * Serial Driver
197  */
198 #define CONFIG_SYS_NS16550_SERIAL
199 #define CONFIG_SYS_NS16550_REG_SIZE	-4
200 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
201 #define CONFIG_SYS_NS16550_CLK		1000000
202 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
203 #define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
204 #define CONFIG_SYS_NS16550_CLK		100000000
205 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
206 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
207 #define CONFIG_SYS_NS16550_CLK		50000000
208 #endif
209 #define CONFIG_CONS_INDEX		1
210 
211 /*
212  * USB
213  */
214 
215 /*
216  * USB Gadget (DFU, UMS)
217  */
218 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
219 #define CONFIG_USB_FUNCTION_MASS_STORAGE
220 
221 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
222 #define DFU_DEFAULT_POLL_TIMEOUT	300
223 
224 /* USB IDs */
225 #define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
226 #define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
227 #endif
228 
229 /*
230  * U-Boot environment
231  */
232 #if !defined(CONFIG_ENV_SIZE)
233 #define CONFIG_ENV_SIZE			(8 * 1024)
234 #endif
235 
236 /* Environment for SDMMC boot */
237 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
238 #define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
239 #define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
240 #endif
241 
242 /* Environment for QSPI boot */
243 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
244 #define CONFIG_ENV_OFFSET		0x00100000
245 #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
246 #endif
247 
248 /*
249  * mtd partitioning for serial NOR flash
250  *
251  * device nor0 <ff705000.spi.0>, # parts = 6
252  * #: name                size            offset          mask_flags
253  * 0: u-boot              0x00100000      0x00000000      0
254  * 1: env1                0x00040000      0x00100000      0
255  * 2: env2                0x00040000      0x00140000      0
256  * 3: UBI                 0x03e80000      0x00180000      0
257  * 4: boot                0x00e80000      0x00180000      0
258  * 5: rootfs              0x01000000      0x01000000      0
259  *
260  */
261 
262 /*
263  * SPL
264  *
265  * SRAM Memory layout:
266  *
267  * 0xFFFF_0000 ...... Start of SRAM
268  * 0xFFFF_xxxx ...... Top of stack (grows down)
269  * 0xFFFF_yyyy ...... Malloc area
270  * 0xFFFF_zzzz ...... Global Data
271  * 0xFFFF_FF00 ...... End of SRAM
272  */
273 #define CONFIG_SPL_FRAMEWORK
274 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
275 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
276 
277 /* SPL SDMMC boot support */
278 #ifdef CONFIG_SPL_MMC_SUPPORT
279 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
280 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
281 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
282 #endif
283 #else
284 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
285 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
286 #endif
287 #endif
288 
289 /* SPL QSPI boot support */
290 #ifdef CONFIG_SPL_SPI_SUPPORT
291 #define CONFIG_SPL_SPI_LOAD
292 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
293 #endif
294 
295 /* SPL NAND boot support */
296 #ifdef CONFIG_SPL_NAND_SUPPORT
297 #define CONFIG_SYS_NAND_USE_FLASH_BBT
298 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
299 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
300 #endif
301 
302 /*
303  * Stack setup
304  */
305 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
306 
307 /* Extra Environment */
308 #ifndef CONFIG_SPL_BUILD
309 #include <config_distro_defaults.h>
310 
311 #ifdef CONFIG_CMD_PXE
312 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
313 #else
314 #define BOOT_TARGET_DEVICES_PXE(func)
315 #endif
316 
317 #ifdef CONFIG_CMD_MMC
318 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
319 #else
320 #define BOOT_TARGET_DEVICES_MMC(func)
321 #endif
322 
323 #define BOOT_TARGET_DEVICES(func) \
324 	BOOT_TARGET_DEVICES_MMC(func) \
325 	BOOT_TARGET_DEVICES_PXE(func) \
326 	func(DHCP, dhcp, na)
327 
328 #include <config_distro_bootcmd.h>
329 
330 #ifndef CONFIG_EXTRA_ENV_SETTINGS
331 #define CONFIG_EXTRA_ENV_SETTINGS \
332 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
333 	"bootm_size=0xa000000\0" \
334 	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
335 	"fdt_addr_r=0x02000000\0" \
336 	"scriptaddr=0x02100000\0" \
337 	"pxefile_addr_r=0x02200000\0" \
338 	"ramdisk_addr_r=0x02300000\0" \
339 	BOOTENV
340 
341 #endif
342 #endif
343 
344 #endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
345