1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 10 /* Virtual target or real hardware */ 11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 12 13 #define CONFIG_SYS_THUMB_BUILD 14 15 /* 16 * High level configuration 17 */ 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO_LATE 20 #define CONFIG_ARCH_MISC_INIT 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_CRC32_VERIFY 26 27 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* add target to build it automatically upon "make" */ 32 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 33 34 /* 35 * Memory configurations 36 */ 37 #define CONFIG_NR_DRAM_BANKS 1 38 #define PHYS_SDRAM_1 0x0 39 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 40 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 41 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 42 43 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 44 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 45 #define CONFIG_SYS_INIT_SP_OFFSET \ 46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 47 #define CONFIG_SYS_INIT_SP_ADDR \ 48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 49 50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 52 #define CONFIG_SYS_TEXT_BASE 0x08000040 53 #else 54 #define CONFIG_SYS_TEXT_BASE 0x01000040 55 #endif 56 57 /* 58 * U-Boot general configurations 59 */ 60 #define CONFIG_SYS_LONGHELP 61 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 62 #define CONFIG_SYS_PBSIZE \ 63 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 64 /* Print buffer size */ 65 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 67 /* Boot argument buffer size */ 68 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 69 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 70 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 71 #define CONFIG_SYS_HUSH_PARSER 72 73 #ifndef CONFIG_SYS_HOSTNAME 74 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 75 #endif 76 77 /* 78 * Cache 79 */ 80 #define CONFIG_SYS_CACHELINE_SIZE 32 81 #define CONFIG_SYS_L2_PL310 82 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 83 84 /* 85 * SDRAM controller 86 */ 87 #define CONFIG_ALTERA_SDRAM 88 89 /* 90 * EPCS/EPCQx1 Serial Flash Controller 91 */ 92 #ifdef CONFIG_ALTERA_SPI 93 #define CONFIG_CMD_SPI 94 #define CONFIG_CMD_SF 95 #define CONFIG_SF_DEFAULT_SPEED 30000000 96 #define CONFIG_SPI_FLASH_BAR 97 /* 98 * The base address is configurable in QSys, each board must specify the 99 * base address based on it's particular FPGA configuration. Please note 100 * that the address here is incremented by 0x400 from the Base address 101 * selected in QSys, since the SPI registers are at offset +0x400. 102 * #define CONFIG_SYS_SPI_BASE 0xff240400 103 */ 104 #endif 105 106 /* 107 * Ethernet on SoC (EMAC) 108 */ 109 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 110 #define CONFIG_DW_ALTDESCRIPTOR 111 #define CONFIG_MII 112 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 113 #define CONFIG_PHY_GIGE 114 #endif 115 116 /* 117 * FPGA Driver 118 */ 119 #ifdef CONFIG_CMD_FPGA 120 #define CONFIG_FPGA 121 #define CONFIG_FPGA_ALTERA 122 #define CONFIG_FPGA_SOCFPGA 123 #define CONFIG_FPGA_COUNT 1 124 #endif 125 126 /* 127 * L4 OSC1 Timer 0 128 */ 129 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 130 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 131 #define CONFIG_SYS_TIMER_COUNTS_DOWN 132 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 133 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 134 #define CONFIG_SYS_TIMER_RATE 2400000 135 #else 136 #define CONFIG_SYS_TIMER_RATE 25000000 137 #endif 138 139 /* 140 * L4 Watchdog 141 */ 142 #ifdef CONFIG_HW_WATCHDOG 143 #define CONFIG_DESIGNWARE_WATCHDOG 144 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 145 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 146 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 147 #endif 148 149 /* 150 * MMC Driver 151 */ 152 #ifdef CONFIG_CMD_MMC 153 #define CONFIG_MMC 154 #define CONFIG_BOUNCE_BUFFER 155 #define CONFIG_GENERIC_MMC 156 #define CONFIG_DWMMC 157 #define CONFIG_SOCFPGA_DWMMC 158 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 159 /* FIXME */ 160 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 161 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 162 #endif 163 164 /* 165 * NAND Support 166 */ 167 #ifdef CONFIG_NAND_DENALI 168 #define CONFIG_SYS_MAX_NAND_DEVICE 1 169 #define CONFIG_SYS_NAND_MAX_CHIPS 1 170 #define CONFIG_SYS_NAND_ONFI_DETECTION 171 #define CONFIG_NAND_DENALI_ECC_SIZE 512 172 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 173 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 174 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 175 #endif 176 177 /* 178 * I2C support 179 */ 180 #define CONFIG_SYS_I2C 181 #define CONFIG_SYS_I2C_DW 182 #define CONFIG_SYS_I2C_BUS_MAX 4 183 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 184 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 185 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 186 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 187 /* Using standard mode which the speed up to 100Kb/s */ 188 #define CONFIG_SYS_I2C_SPEED 100000 189 #define CONFIG_SYS_I2C_SPEED1 100000 190 #define CONFIG_SYS_I2C_SPEED2 100000 191 #define CONFIG_SYS_I2C_SPEED3 100000 192 /* Address of device when used as slave */ 193 #define CONFIG_SYS_I2C_SLAVE 0x02 194 #define CONFIG_SYS_I2C_SLAVE1 0x02 195 #define CONFIG_SYS_I2C_SLAVE2 0x02 196 #define CONFIG_SYS_I2C_SLAVE3 0x02 197 #ifndef __ASSEMBLY__ 198 /* Clock supplied to I2C controller in unit of MHz */ 199 unsigned int cm_get_l4_sp_clk_hz(void); 200 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 201 #endif 202 #define CONFIG_CMD_I2C 203 204 /* 205 * QSPI support 206 */ 207 /* Enable multiple SPI NOR flash manufacturers */ 208 #ifndef CONFIG_SPL_BUILD 209 #define CONFIG_SPI_FLASH_MTD 210 #define CONFIG_CMD_MTDPARTS 211 #define CONFIG_MTD_DEVICE 212 #define CONFIG_MTD_PARTITIONS 213 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 214 #endif 215 /* QSPI reference clock */ 216 #ifndef __ASSEMBLY__ 217 unsigned int cm_get_qspi_controller_clk_hz(void); 218 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 219 #endif 220 #define CONFIG_CQSPI_DECODER 0 221 #define CONFIG_CMD_SF 222 #define CONFIG_SPI_FLASH_BAR 223 224 /* 225 * Designware SPI support 226 */ 227 #define CONFIG_CMD_SPI 228 229 /* 230 * Serial Driver 231 */ 232 #define CONFIG_SYS_NS16550_SERIAL 233 #define CONFIG_SYS_NS16550_REG_SIZE -4 234 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 235 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 236 #define CONFIG_SYS_NS16550_CLK 1000000 237 #else 238 #define CONFIG_SYS_NS16550_CLK 100000000 239 #endif 240 #define CONFIG_CONS_INDEX 1 241 #define CONFIG_BAUDRATE 115200 242 243 /* 244 * USB 245 */ 246 #ifdef CONFIG_CMD_USB 247 #define CONFIG_USB_DWC2 248 #define CONFIG_USB_STORAGE 249 #endif 250 251 /* 252 * USB Gadget (DFU, UMS) 253 */ 254 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 255 #define CONFIG_USB_GADGET 256 #define CONFIG_USB_GADGET_DWC2_OTG 257 #define CONFIG_USB_GADGET_DUALSPEED 258 #define CONFIG_USB_GADGET_VBUS_DRAW 2 259 260 /* USB Composite download gadget - g_dnl */ 261 #define CONFIG_USB_GADGET_DOWNLOAD 262 #define CONFIG_USB_FUNCTION_MASS_STORAGE 263 264 #define CONFIG_USB_FUNCTION_DFU 265 #ifdef CONFIG_DM_MMC 266 #define CONFIG_DFU_MMC 267 #endif 268 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 269 #define DFU_DEFAULT_POLL_TIMEOUT 300 270 271 /* USB IDs */ 272 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 273 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 274 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 275 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 276 #ifndef CONFIG_G_DNL_MANUFACTURER 277 #define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR 278 #endif 279 #endif 280 281 /* 282 * U-Boot environment 283 */ 284 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 285 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 286 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 287 #define CONFIG_ENV_SIZE 4096 288 289 /* Environment for SDMMC boot */ 290 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 291 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 292 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 293 #endif 294 295 /* 296 * mtd partitioning for serial NOR flash 297 * 298 * device nor0 <ff705000.spi.0>, # parts = 6 299 * #: name size offset mask_flags 300 * 0: u-boot 0x00100000 0x00000000 0 301 * 1: env1 0x00040000 0x00100000 0 302 * 2: env2 0x00040000 0x00140000 0 303 * 3: UBI 0x03e80000 0x00180000 0 304 * 4: boot 0x00e80000 0x00180000 0 305 * 5: rootfs 0x01000000 0x01000000 0 306 * 307 */ 308 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 309 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 310 "1m(u-boot)," \ 311 "256k(env1)," \ 312 "256k(env2)," \ 313 "14848k(boot)," \ 314 "16m(rootfs)," \ 315 "-@1536k(UBI)\0" 316 #endif 317 318 /* UBI and UBIFS support */ 319 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 320 #define CONFIG_CMD_UBI 321 #define CONFIG_CMD_UBIFS 322 #define CONFIG_RBTREE 323 #define CONFIG_LZO 324 #endif 325 326 /* 327 * SPL 328 * 329 * SRAM Memory layout: 330 * 331 * 0xFFFF_0000 ...... Start of SRAM 332 * 0xFFFF_xxxx ...... Top of stack (grows down) 333 * 0xFFFF_yyyy ...... Malloc area 334 * 0xFFFF_zzzz ...... Global Data 335 * 0xFFFF_FF00 ...... End of SRAM 336 */ 337 #define CONFIG_SPL_FRAMEWORK 338 #define CONFIG_SPL_RAM_DEVICE 339 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 340 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 341 #ifdef CONFIG_SPL_BUILD 342 #define CONFIG_SYS_MALLOC_SIMPLE 343 #endif 344 345 #define CONFIG_SPL_LIBCOMMON_SUPPORT 346 #define CONFIG_SPL_LIBGENERIC_SUPPORT 347 #define CONFIG_SPL_WATCHDOG_SUPPORT 348 #define CONFIG_SPL_SERIAL_SUPPORT 349 #ifdef CONFIG_DM_MMC 350 #define CONFIG_SPL_MMC_SUPPORT 351 #endif 352 #ifdef CONFIG_DM_SPI 353 #define CONFIG_SPL_SPI_SUPPORT 354 #endif 355 #ifdef CONFIG_SPL_NAND_DENALI 356 #define CONFIG_SPL_NAND_SUPPORT 357 #endif 358 359 /* SPL SDMMC boot support */ 360 #ifdef CONFIG_SPL_MMC_SUPPORT 361 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 362 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 363 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 364 #define CONFIG_SPL_LIBDISK_SUPPORT 365 #else 366 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 367 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 368 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 369 #endif 370 #endif 371 372 /* SPL QSPI boot support */ 373 #ifdef CONFIG_SPL_SPI_SUPPORT 374 #define CONFIG_SPL_SPI_FLASH_SUPPORT 375 #define CONFIG_SPL_SPI_LOAD 376 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 377 #endif 378 379 /* SPL NAND boot support */ 380 #ifdef CONFIG_SPL_NAND_SUPPORT 381 #define CONFIG_SYS_NAND_USE_FLASH_BBT 382 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 383 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 384 #endif 385 386 /* 387 * Stack setup 388 */ 389 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 390 391 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 392