1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* 18 * Memory configurations 19 */ 20 #define PHYS_SDRAM_1 0x0 21 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 22 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 23 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 24 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 25 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 26 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 27 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 29 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 30 #endif 31 32 /* 33 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 34 * SRAM as bootcounter storage. Make sure to not put the stack directly 35 * at this address to not overwrite the bootcounter by checking, if the 36 * bootcounter address is located in the internal SRAM. 37 */ 38 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 39 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 40 CONFIG_SYS_INIT_RAM_SIZE))) 41 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR 42 #else 43 #define CONFIG_SYS_INIT_SP_ADDR \ 44 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 45 #endif 46 47 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 48 49 /* 50 * U-Boot general configurations 51 */ 52 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 53 /* Print buffer size */ 54 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 55 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 56 /* Boot argument buffer size */ 57 58 #ifndef CONFIG_SYS_HOSTNAME 59 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 60 #endif 61 62 /* 63 * Cache 64 */ 65 #define CONFIG_SYS_L2_PL310 66 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 67 68 /* 69 * EPCS/EPCQx1 Serial Flash Controller 70 */ 71 #ifdef CONFIG_ALTERA_SPI 72 /* 73 * The base address is configurable in QSys, each board must specify the 74 * base address based on it's particular FPGA configuration. Please note 75 * that the address here is incremented by 0x400 from the Base address 76 * selected in QSys, since the SPI registers are at offset +0x400. 77 * #define CONFIG_SYS_SPI_BASE 0xff240400 78 */ 79 #endif 80 81 /* 82 * Ethernet on SoC (EMAC) 83 */ 84 #ifdef CONFIG_CMD_NET 85 #define CONFIG_DW_ALTDESCRIPTOR 86 #endif 87 88 /* 89 * FPGA Driver 90 */ 91 #ifdef CONFIG_CMD_FPGA 92 #define CONFIG_FPGA_COUNT 1 93 #endif 94 95 /* 96 * L4 OSC1 Timer 0 97 */ 98 #ifndef CONFIG_TIMER 99 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 100 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 101 #define CONFIG_SYS_TIMER_COUNTS_DOWN 102 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 103 #define CONFIG_SYS_TIMER_RATE 25000000 104 #endif 105 106 /* 107 * L4 Watchdog 108 */ 109 #ifdef CONFIG_HW_WATCHDOG 110 #define CONFIG_DESIGNWARE_WATCHDOG 111 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 112 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 113 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 114 #endif 115 116 /* 117 * MMC Driver 118 */ 119 #ifdef CONFIG_CMD_MMC 120 /* FIXME */ 121 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 122 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 123 #endif 124 125 /* 126 * NAND Support 127 */ 128 #ifdef CONFIG_NAND_DENALI 129 #define CONFIG_SYS_MAX_NAND_DEVICE 1 130 #define CONFIG_SYS_NAND_ONFI_DETECTION 131 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 132 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 133 #endif 134 135 /* 136 * I2C support 137 */ 138 #ifndef CONFIG_DM_I2C 139 #define CONFIG_SYS_I2C 140 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 141 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 142 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 143 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 144 /* Using standard mode which the speed up to 100Kb/s */ 145 #define CONFIG_SYS_I2C_SPEED 100000 146 #define CONFIG_SYS_I2C_SPEED1 100000 147 #define CONFIG_SYS_I2C_SPEED2 100000 148 #define CONFIG_SYS_I2C_SPEED3 100000 149 /* Address of device when used as slave */ 150 #define CONFIG_SYS_I2C_SLAVE 0x02 151 #define CONFIG_SYS_I2C_SLAVE1 0x02 152 #define CONFIG_SYS_I2C_SLAVE2 0x02 153 #define CONFIG_SYS_I2C_SLAVE3 0x02 154 #ifndef __ASSEMBLY__ 155 /* Clock supplied to I2C controller in unit of MHz */ 156 unsigned int cm_get_l4_sp_clk_hz(void); 157 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 158 #endif 159 #endif /* CONFIG_DM_I2C */ 160 161 /* 162 * QSPI support 163 */ 164 /* Enable multiple SPI NOR flash manufacturers */ 165 #ifndef CONFIG_SPL_BUILD 166 #define CONFIG_SPI_FLASH_MTD 167 #endif 168 /* QSPI reference clock */ 169 #ifndef __ASSEMBLY__ 170 unsigned int cm_get_qspi_controller_clk_hz(void); 171 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 172 #endif 173 174 /* 175 * Designware SPI support 176 */ 177 178 /* 179 * Serial Driver 180 */ 181 #define CONFIG_SYS_NS16550_SERIAL 182 183 /* 184 * USB 185 */ 186 187 /* 188 * USB Gadget (DFU, UMS) 189 */ 190 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 191 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 192 #define DFU_DEFAULT_POLL_TIMEOUT 300 193 194 /* USB IDs */ 195 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 196 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 197 #endif 198 199 /* 200 * U-Boot environment 201 */ 202 #if !defined(CONFIG_ENV_SIZE) 203 #define CONFIG_ENV_SIZE (8 * 1024) 204 #endif 205 206 /* Environment for SDMMC boot */ 207 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 208 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 209 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 210 #endif 211 212 /* Environment for QSPI boot */ 213 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 214 #define CONFIG_ENV_OFFSET 0x00100000 215 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 216 #endif 217 218 /* 219 * mtd partitioning for serial NOR flash 220 * 221 * device nor0 <ff705000.spi.0>, # parts = 6 222 * #: name size offset mask_flags 223 * 0: u-boot 0x00100000 0x00000000 0 224 * 1: env1 0x00040000 0x00100000 0 225 * 2: env2 0x00040000 0x00140000 0 226 * 3: UBI 0x03e80000 0x00180000 0 227 * 4: boot 0x00e80000 0x00180000 0 228 * 5: rootfs 0x01000000 0x01000000 0 229 * 230 */ 231 232 /* 233 * SPL 234 * 235 * SRAM Memory layout for gen 5: 236 * 237 * 0xFFFF_0000 ...... Start of SRAM 238 * 0xFFFF_xxxx ...... Top of stack (grows down) 239 * 0xFFFF_yyyy ...... Malloc area 240 * 0xFFFF_zzzz ...... Global Data 241 * 0xFFFF_FF00 ...... End of SRAM 242 * 243 * SRAM Memory layout for Arria 10: 244 * 0xFFE0_0000 ...... Start of SRAM (bottom) 245 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 246 * 0xFFEy_yyyy ...... Global Data 247 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 248 * 0xFFE3_FFFF ...... End of SRAM (top) 249 */ 250 #ifndef CONFIG_SPL_TEXT_BASE 251 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 252 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 253 #endif 254 255 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 256 /* SPL memory allocation configuration, this is for FAT implementation */ 257 #ifndef CONFIG_SYS_SPL_MALLOC_START 258 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 259 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 260 CONFIG_SYS_SPL_MALLOC_SIZE + \ 261 CONFIG_SYS_INIT_RAM_ADDR) 262 #endif 263 #endif 264 265 /* SPL SDMMC boot support */ 266 #ifdef CONFIG_SPL_MMC_SUPPORT 267 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 268 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 269 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 270 #endif 271 #else 272 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 273 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 274 #endif 275 #endif 276 277 /* SPL QSPI boot support */ 278 #ifdef CONFIG_SPL_SPI_SUPPORT 279 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 280 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 281 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 282 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 283 #endif 284 #endif 285 286 /* SPL NAND boot support */ 287 #ifdef CONFIG_SPL_NAND_SUPPORT 288 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 289 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 290 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 291 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 292 #endif 293 #endif 294 295 /* 296 * Stack setup 297 */ 298 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 299 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 300 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 301 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 302 #endif 303 304 /* Extra Environment */ 305 #ifndef CONFIG_SPL_BUILD 306 307 #ifdef CONFIG_CMD_DHCP 308 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 309 #else 310 #define BOOT_TARGET_DEVICES_DHCP(func) 311 #endif 312 313 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 314 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 315 #else 316 #define BOOT_TARGET_DEVICES_PXE(func) 317 #endif 318 319 #ifdef CONFIG_CMD_MMC 320 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 321 #else 322 #define BOOT_TARGET_DEVICES_MMC(func) 323 #endif 324 325 #define BOOT_TARGET_DEVICES(func) \ 326 BOOT_TARGET_DEVICES_MMC(func) \ 327 BOOT_TARGET_DEVICES_PXE(func) \ 328 BOOT_TARGET_DEVICES_DHCP(func) 329 330 #include <config_distro_bootcmd.h> 331 332 #ifndef CONFIG_EXTRA_ENV_SETTINGS 333 #define CONFIG_EXTRA_ENV_SETTINGS \ 334 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 335 "bootm_size=0xa000000\0" \ 336 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 337 "fdt_addr_r=0x02000000\0" \ 338 "scriptaddr=0x02100000\0" \ 339 "pxefile_addr_r=0x02200000\0" \ 340 "ramdisk_addr_r=0x02300000\0" \ 341 BOOTENV 342 343 #endif 344 #endif 345 346 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 347