1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22 /* add target to build it automatically upon "make" */ 23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25 /* 26 * Memory configurations 27 */ 28 #define CONFIG_NR_DRAM_BANKS 1 29 #define PHYS_SDRAM_1 0x0 30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39 #endif 40 #define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 47 #define CONFIG_SYS_TEXT_BASE 0x08000040 48 #else 49 #define CONFIG_SYS_TEXT_BASE 0x01000040 50 #endif 51 52 /* 53 * U-Boot general configurations 54 */ 55 #define CONFIG_SYS_LONGHELP 56 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 57 #define CONFIG_SYS_PBSIZE \ 58 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 59 /* Print buffer size */ 60 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 61 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 62 /* Boot argument buffer size */ 63 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 64 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 65 66 #ifndef CONFIG_SYS_HOSTNAME 67 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 68 #endif 69 70 #define CONFIG_CMD_PXE 71 #define CONFIG_MENU 72 73 /* 74 * Cache 75 */ 76 #define CONFIG_SYS_L2_PL310 77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 78 79 /* 80 * EPCS/EPCQx1 Serial Flash Controller 81 */ 82 #ifdef CONFIG_ALTERA_SPI 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 /* 85 * The base address is configurable in QSys, each board must specify the 86 * base address based on it's particular FPGA configuration. Please note 87 * that the address here is incremented by 0x400 from the Base address 88 * selected in QSys, since the SPI registers are at offset +0x400. 89 * #define CONFIG_SYS_SPI_BASE 0xff240400 90 */ 91 #endif 92 93 /* 94 * Ethernet on SoC (EMAC) 95 */ 96 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 97 #define CONFIG_DW_ALTDESCRIPTOR 98 #define CONFIG_MII 99 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 100 #define CONFIG_PHY_GIGE 101 #endif 102 103 /* 104 * FPGA Driver 105 */ 106 #ifdef CONFIG_CMD_FPGA 107 #define CONFIG_FPGA_COUNT 1 108 #endif 109 110 /* 111 * L4 OSC1 Timer 0 112 */ 113 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 114 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 115 #define CONFIG_SYS_TIMER_COUNTS_DOWN 116 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 117 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 118 #define CONFIG_SYS_TIMER_RATE 2400000 119 #else 120 #define CONFIG_SYS_TIMER_RATE 25000000 121 #endif 122 123 /* 124 * L4 Watchdog 125 */ 126 #ifdef CONFIG_HW_WATCHDOG 127 #define CONFIG_DESIGNWARE_WATCHDOG 128 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 129 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 130 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 131 #endif 132 133 /* 134 * MMC Driver 135 */ 136 #ifdef CONFIG_CMD_MMC 137 #define CONFIG_BOUNCE_BUFFER 138 /* FIXME */ 139 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 140 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 141 #endif 142 143 /* 144 * NAND Support 145 */ 146 #ifdef CONFIG_NAND_DENALI 147 #define CONFIG_SYS_MAX_NAND_DEVICE 1 148 #define CONFIG_SYS_NAND_MAX_CHIPS 1 149 #define CONFIG_SYS_NAND_ONFI_DETECTION 150 #define CONFIG_NAND_DENALI_ECC_SIZE 512 151 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 152 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 153 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 154 #endif 155 156 /* 157 * I2C support 158 */ 159 #define CONFIG_SYS_I2C 160 #define CONFIG_SYS_I2C_BUS_MAX 4 161 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 162 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 163 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 164 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 165 /* Using standard mode which the speed up to 100Kb/s */ 166 #define CONFIG_SYS_I2C_SPEED 100000 167 #define CONFIG_SYS_I2C_SPEED1 100000 168 #define CONFIG_SYS_I2C_SPEED2 100000 169 #define CONFIG_SYS_I2C_SPEED3 100000 170 /* Address of device when used as slave */ 171 #define CONFIG_SYS_I2C_SLAVE 0x02 172 #define CONFIG_SYS_I2C_SLAVE1 0x02 173 #define CONFIG_SYS_I2C_SLAVE2 0x02 174 #define CONFIG_SYS_I2C_SLAVE3 0x02 175 #ifndef __ASSEMBLY__ 176 /* Clock supplied to I2C controller in unit of MHz */ 177 unsigned int cm_get_l4_sp_clk_hz(void); 178 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 179 #endif 180 181 /* 182 * QSPI support 183 */ 184 /* Enable multiple SPI NOR flash manufacturers */ 185 #ifndef CONFIG_SPL_BUILD 186 #define CONFIG_SPI_FLASH_MTD 187 #define CONFIG_MTD_DEVICE 188 #define CONFIG_MTD_PARTITIONS 189 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 190 #endif 191 /* QSPI reference clock */ 192 #ifndef __ASSEMBLY__ 193 unsigned int cm_get_qspi_controller_clk_hz(void); 194 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 195 #endif 196 #define CONFIG_CQSPI_DECODER 0 197 #define CONFIG_BOUNCE_BUFFER 198 199 /* 200 * Designware SPI support 201 */ 202 203 /* 204 * Serial Driver 205 */ 206 #define CONFIG_SYS_NS16550_SERIAL 207 #define CONFIG_SYS_NS16550_REG_SIZE -4 208 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 209 #define CONFIG_SYS_NS16550_CLK 1000000 210 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 211 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 212 #define CONFIG_SYS_NS16550_CLK 100000000 213 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 214 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 215 #define CONFIG_SYS_NS16550_CLK 50000000 216 #endif 217 #define CONFIG_CONS_INDEX 1 218 219 /* 220 * USB 221 */ 222 223 /* 224 * USB Gadget (DFU, UMS) 225 */ 226 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 227 #define CONFIG_USB_FUNCTION_MASS_STORAGE 228 229 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 230 #define DFU_DEFAULT_POLL_TIMEOUT 300 231 232 /* USB IDs */ 233 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 234 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 235 #endif 236 237 /* 238 * U-Boot environment 239 */ 240 #if !defined(CONFIG_ENV_SIZE) 241 #define CONFIG_ENV_SIZE (8 * 1024) 242 #endif 243 244 /* Environment for SDMMC boot */ 245 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 246 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 247 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 248 #endif 249 250 /* Environment for QSPI boot */ 251 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 252 #define CONFIG_ENV_OFFSET 0x00100000 253 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 254 #endif 255 256 /* 257 * mtd partitioning for serial NOR flash 258 * 259 * device nor0 <ff705000.spi.0>, # parts = 6 260 * #: name size offset mask_flags 261 * 0: u-boot 0x00100000 0x00000000 0 262 * 1: env1 0x00040000 0x00100000 0 263 * 2: env2 0x00040000 0x00140000 0 264 * 3: UBI 0x03e80000 0x00180000 0 265 * 4: boot 0x00e80000 0x00180000 0 266 * 5: rootfs 0x01000000 0x01000000 0 267 * 268 */ 269 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 270 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 271 "1m(u-boot)," \ 272 "256k(env1)," \ 273 "256k(env2)," \ 274 "14848k(boot)," \ 275 "16m(rootfs)," \ 276 "-@1536k(UBI)\0" 277 #endif 278 279 /* 280 * SPL 281 * 282 * SRAM Memory layout: 283 * 284 * 0xFFFF_0000 ...... Start of SRAM 285 * 0xFFFF_xxxx ...... Top of stack (grows down) 286 * 0xFFFF_yyyy ...... Malloc area 287 * 0xFFFF_zzzz ...... Global Data 288 * 0xFFFF_FF00 ...... End of SRAM 289 */ 290 #define CONFIG_SPL_FRAMEWORK 291 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 292 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 293 294 /* SPL SDMMC boot support */ 295 #ifdef CONFIG_SPL_MMC_SUPPORT 296 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 297 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 298 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 299 #endif 300 #else 301 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 302 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 303 #endif 304 #endif 305 306 /* SPL QSPI boot support */ 307 #ifdef CONFIG_SPL_SPI_SUPPORT 308 #define CONFIG_SPL_SPI_LOAD 309 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 310 #endif 311 312 /* SPL NAND boot support */ 313 #ifdef CONFIG_SPL_NAND_SUPPORT 314 #define CONFIG_SYS_NAND_USE_FLASH_BBT 315 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 316 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 317 #endif 318 319 /* 320 * Stack setup 321 */ 322 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 323 324 /* Extra Environment */ 325 #ifndef CONFIG_SPL_BUILD 326 #include <config_distro_defaults.h> 327 328 #ifdef CONFIG_CMD_PXE 329 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 330 #else 331 #define BOOT_TARGET_DEVICES_PXE(func) 332 #endif 333 334 #ifdef CONFIG_CMD_MMC 335 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 336 #else 337 #define BOOT_TARGET_DEVICES_MMC(func) 338 #endif 339 340 #define BOOT_TARGET_DEVICES(func) \ 341 BOOT_TARGET_DEVICES_MMC(func) \ 342 BOOT_TARGET_DEVICES_PXE(func) \ 343 func(DHCP, dhcp, na) 344 345 #include <config_distro_bootcmd.h> 346 347 #ifndef CONFIG_EXTRA_ENV_SETTINGS 348 #define CONFIG_EXTRA_ENV_SETTINGS \ 349 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 350 "bootm_size=0xa000000\0" \ 351 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 352 "fdt_addr_r=0x02000000\0" \ 353 "scriptaddr=0x02100000\0" \ 354 "pxefile_addr_r=0x02200000\0" \ 355 "ramdisk_addr_r=0x02300000\0" \ 356 BOOTENV 357 358 #endif 359 #endif 360 361 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 362