1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_CRC32_VERIFY 19 20 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 21 22 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 23 24 /* add target to build it automatically upon "make" */ 25 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 26 27 /* 28 * Memory configurations 29 */ 30 #define CONFIG_NR_DRAM_BANKS 1 31 #define PHYS_SDRAM_1 0x0 32 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 33 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 34 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 35 36 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 37 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 38 #define CONFIG_SYS_INIT_SP_OFFSET \ 39 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 40 #define CONFIG_SYS_INIT_SP_ADDR \ 41 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 42 43 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 44 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 45 #define CONFIG_SYS_TEXT_BASE 0x08000040 46 #else 47 #define CONFIG_SYS_TEXT_BASE 0x01000040 48 #endif 49 50 /* 51 * U-Boot general configurations 52 */ 53 #define CONFIG_SYS_LONGHELP 54 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 55 #define CONFIG_SYS_PBSIZE \ 56 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 57 /* Print buffer size */ 58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 60 /* Boot argument buffer size */ 61 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 62 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 63 64 #ifndef CONFIG_SYS_HOSTNAME 65 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 66 #endif 67 68 #define CONFIG_CMD_PXE 69 #define CONFIG_MENU 70 71 /* 72 * Cache 73 */ 74 #define CONFIG_SYS_L2_PL310 75 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 76 77 /* 78 * EPCS/EPCQx1 Serial Flash Controller 79 */ 80 #ifdef CONFIG_ALTERA_SPI 81 #define CONFIG_SF_DEFAULT_SPEED 30000000 82 /* 83 * The base address is configurable in QSys, each board must specify the 84 * base address based on it's particular FPGA configuration. Please note 85 * that the address here is incremented by 0x400 from the Base address 86 * selected in QSys, since the SPI registers are at offset +0x400. 87 * #define CONFIG_SYS_SPI_BASE 0xff240400 88 */ 89 #endif 90 91 /* 92 * Ethernet on SoC (EMAC) 93 */ 94 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 95 #define CONFIG_DW_ALTDESCRIPTOR 96 #define CONFIG_MII 97 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 98 #define CONFIG_PHY_GIGE 99 #endif 100 101 /* 102 * FPGA Driver 103 */ 104 #ifdef CONFIG_CMD_FPGA 105 #define CONFIG_FPGA 106 #define CONFIG_FPGA_ALTERA 107 #define CONFIG_FPGA_SOCFPGA 108 #define CONFIG_FPGA_COUNT 1 109 #endif 110 111 /* 112 * L4 OSC1 Timer 0 113 */ 114 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 115 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 116 #define CONFIG_SYS_TIMER_COUNTS_DOWN 117 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 118 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 119 #define CONFIG_SYS_TIMER_RATE 2400000 120 #else 121 #define CONFIG_SYS_TIMER_RATE 25000000 122 #endif 123 124 /* 125 * L4 Watchdog 126 */ 127 #ifdef CONFIG_HW_WATCHDOG 128 #define CONFIG_DESIGNWARE_WATCHDOG 129 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 130 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 131 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 132 #endif 133 134 /* 135 * MMC Driver 136 */ 137 #ifdef CONFIG_CMD_MMC 138 #define CONFIG_BOUNCE_BUFFER 139 /* FIXME */ 140 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 141 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 142 #endif 143 144 /* 145 * NAND Support 146 */ 147 #ifdef CONFIG_NAND_DENALI 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 149 #define CONFIG_SYS_NAND_MAX_CHIPS 1 150 #define CONFIG_SYS_NAND_ONFI_DETECTION 151 #define CONFIG_NAND_DENALI_ECC_SIZE 512 152 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 153 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 154 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 155 #endif 156 157 /* 158 * I2C support 159 */ 160 #define CONFIG_SYS_I2C 161 #define CONFIG_SYS_I2C_BUS_MAX 4 162 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 163 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 164 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 165 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 166 /* Using standard mode which the speed up to 100Kb/s */ 167 #define CONFIG_SYS_I2C_SPEED 100000 168 #define CONFIG_SYS_I2C_SPEED1 100000 169 #define CONFIG_SYS_I2C_SPEED2 100000 170 #define CONFIG_SYS_I2C_SPEED3 100000 171 /* Address of device when used as slave */ 172 #define CONFIG_SYS_I2C_SLAVE 0x02 173 #define CONFIG_SYS_I2C_SLAVE1 0x02 174 #define CONFIG_SYS_I2C_SLAVE2 0x02 175 #define CONFIG_SYS_I2C_SLAVE3 0x02 176 #ifndef __ASSEMBLY__ 177 /* Clock supplied to I2C controller in unit of MHz */ 178 unsigned int cm_get_l4_sp_clk_hz(void); 179 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 180 #endif 181 182 /* 183 * QSPI support 184 */ 185 /* Enable multiple SPI NOR flash manufacturers */ 186 #ifndef CONFIG_SPL_BUILD 187 #define CONFIG_SPI_FLASH_MTD 188 #define CONFIG_CMD_MTDPARTS 189 #define CONFIG_MTD_DEVICE 190 #define CONFIG_MTD_PARTITIONS 191 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 192 #endif 193 /* QSPI reference clock */ 194 #ifndef __ASSEMBLY__ 195 unsigned int cm_get_qspi_controller_clk_hz(void); 196 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 197 #endif 198 #define CONFIG_CQSPI_DECODER 0 199 #define CONFIG_BOUNCE_BUFFER 200 201 /* 202 * Designware SPI support 203 */ 204 205 /* 206 * Serial Driver 207 */ 208 #define CONFIG_SYS_NS16550_SERIAL 209 #define CONFIG_SYS_NS16550_REG_SIZE -4 210 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 211 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 212 #define CONFIG_SYS_NS16550_CLK 1000000 213 #else 214 #define CONFIG_SYS_NS16550_CLK 100000000 215 #endif 216 #define CONFIG_CONS_INDEX 1 217 218 /* 219 * USB 220 */ 221 #ifdef CONFIG_CMD_USB 222 #define CONFIG_USB_DWC2 223 #endif 224 225 /* 226 * USB Gadget (DFU, UMS) 227 */ 228 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 229 #define CONFIG_USB_FUNCTION_MASS_STORAGE 230 231 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 232 #define DFU_DEFAULT_POLL_TIMEOUT 300 233 234 /* USB IDs */ 235 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 236 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 237 #endif 238 239 /* 240 * U-Boot environment 241 */ 242 #if !defined(CONFIG_ENV_SIZE) 243 #define CONFIG_ENV_SIZE (8 * 1024) 244 #endif 245 246 /* Environment for SDMMC boot */ 247 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 248 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 249 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 250 #endif 251 252 /* Environment for QSPI boot */ 253 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 254 #define CONFIG_ENV_OFFSET 0x00100000 255 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 256 #endif 257 258 /* 259 * mtd partitioning for serial NOR flash 260 * 261 * device nor0 <ff705000.spi.0>, # parts = 6 262 * #: name size offset mask_flags 263 * 0: u-boot 0x00100000 0x00000000 0 264 * 1: env1 0x00040000 0x00100000 0 265 * 2: env2 0x00040000 0x00140000 0 266 * 3: UBI 0x03e80000 0x00180000 0 267 * 4: boot 0x00e80000 0x00180000 0 268 * 5: rootfs 0x01000000 0x01000000 0 269 * 270 */ 271 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 272 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 273 "1m(u-boot)," \ 274 "256k(env1)," \ 275 "256k(env2)," \ 276 "14848k(boot)," \ 277 "16m(rootfs)," \ 278 "-@1536k(UBI)\0" 279 #endif 280 281 /* UBI and UBIFS support */ 282 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 283 #define CONFIG_CMD_UBIFS 284 #define CONFIG_RBTREE 285 #define CONFIG_LZO 286 #endif 287 288 /* 289 * SPL 290 * 291 * SRAM Memory layout: 292 * 293 * 0xFFFF_0000 ...... Start of SRAM 294 * 0xFFFF_xxxx ...... Top of stack (grows down) 295 * 0xFFFF_yyyy ...... Malloc area 296 * 0xFFFF_zzzz ...... Global Data 297 * 0xFFFF_FF00 ...... End of SRAM 298 */ 299 #define CONFIG_SPL_FRAMEWORK 300 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 301 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 302 303 /* SPL SDMMC boot support */ 304 #ifdef CONFIG_SPL_MMC_SUPPORT 305 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 306 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 307 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 308 #endif 309 #else 310 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 311 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 312 #endif 313 #endif 314 315 /* SPL QSPI boot support */ 316 #ifdef CONFIG_SPL_SPI_SUPPORT 317 #define CONFIG_SPL_SPI_LOAD 318 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 319 #endif 320 321 /* SPL NAND boot support */ 322 #ifdef CONFIG_SPL_NAND_SUPPORT 323 #define CONFIG_SYS_NAND_USE_FLASH_BBT 324 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 325 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 326 #endif 327 328 /* 329 * Stack setup 330 */ 331 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 332 333 /* Extra Environment */ 334 #ifndef CONFIG_SPL_BUILD 335 #include <config_distro_defaults.h> 336 337 #ifdef CONFIG_CMD_PXE 338 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 339 #else 340 #define BOOT_TARGET_DEVICES_PXE(func) 341 #endif 342 343 #ifdef CONFIG_CMD_MMC 344 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 345 #else 346 #define BOOT_TARGET_DEVICES_MMC(func) 347 #endif 348 349 #define BOOT_TARGET_DEVICES(func) \ 350 BOOT_TARGET_DEVICES_MMC(func) \ 351 BOOT_TARGET_DEVICES_PXE(func) \ 352 func(DHCP, dhcp, na) 353 354 #include <config_distro_bootcmd.h> 355 356 #ifndef CONFIG_EXTRA_ENV_SETTINGS 357 #define CONFIG_EXTRA_ENV_SETTINGS \ 358 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 359 "bootm_size=0xa000000\0" \ 360 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 361 "fdt_addr_r=0x02000000\0" \ 362 "scriptaddr=0x02100000\0" \ 363 "pxefile_addr_r=0x02200000\0" \ 364 "ramdisk_addr_r=0x02300000\0" \ 365 BOOTENV 366 367 #endif 368 #endif 369 370 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 371