1 /* 2 * Bluewater Systems Snapper 9260 and 9G20 modules 3 * 4 * (C) Copyright 2011 Bluewater Systems 5 * Author: Andre Renaud <andre@bluewatersys.com> 6 * Author: Ryan Mallon <ryan@bluewatersys.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* SoC type is defined in boards.cfg */ 15 #include <asm/hardware.h> 16 #include <linux/sizes.h> 17 18 /* ARM asynchronous clock */ 19 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ 20 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 21 22 /* CPU */ 23 #define CONFIG_ARCH_CPU_INIT 24 25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_INITRD_TAG 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 /* SDRAM */ 31 #define CONFIG_NR_DRAM_BANKS 1 32 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 33 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ 34 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ 35 GENERATED_GBL_DATA_SIZE) 36 37 /* Mem test settings */ 38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 39 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) 40 41 /* NAND Flash */ 42 #define CONFIG_NAND_ATMEL 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 45 #define CONFIG_SYS_NAND_DBW_8 46 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ 47 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ 48 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 49 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 50 51 /* Ethernet */ 52 #define CONFIG_MACB 53 #define CONFIG_RMII 54 #define CONFIG_NET_RETRY_COUNT 20 55 #define CONFIG_RESET_PHY_R 56 #define CONFIG_AT91_WANTS_COMMON_PHY 57 #define CONFIG_TFTP_PORT 58 #define CONFIG_TFTP_TSIZE 59 60 /* USB */ 61 #define CONFIG_USB_ATMEL 62 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 63 #define CONFIG_USB_OHCI_NEW 64 #define CONFIG_SYS_USB_OHCI_CPU_INIT 65 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE 66 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" 67 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 68 69 /* GPIOs and IO expander */ 70 #define CONFIG_ATMEL_LEGACY 71 #define CONFIG_AT91_GPIO 72 #define CONFIG_AT91_GPIO_PULLUP 1 73 #define CONFIG_PCA953X 74 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 75 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } 76 77 /* UARTs/Serial console */ 78 #define CONFIG_ATMEL_USART 79 #ifndef CONFIG_DM_SERIAL 80 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 81 #define CONFIG_USART_ID ATMEL_ID_SYS 82 #endif 83 84 /* I2C - Bit-bashed */ 85 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 87 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 88 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 89 #define CONFIG_SOFT_I2C_READ_REPEATED_START 90 #define I2C_INIT do { \ 91 at91_set_gpio_output(AT91_PIN_PA23, 1); \ 92 at91_set_gpio_output(AT91_PIN_PA24, 1); \ 93 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 94 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 95 } while (0) 96 #define I2C_SOFT_DECLARATIONS 97 #define I2C_ACTIVE 98 #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); 99 #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); 100 #define I2C_SDA(bit) do { \ 101 if (bit) { \ 102 at91_set_gpio_input(AT91_PIN_PA23, 1); \ 103 } else { \ 104 at91_set_gpio_output(AT91_PIN_PA23, 1); \ 105 at91_set_gpio_value(AT91_PIN_PA23, bit); \ 106 } \ 107 } while (0) 108 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 109 #define I2C_DELAY udelay(2) 110 111 /* Boot options */ 112 #define CONFIG_SYS_LOAD_ADDR 0x23000000 113 114 #define CONFIG_BOOTP_BOOTFILESIZE 115 116 /* Environment settings */ 117 #define CONFIG_ENV_OFFSET (512 << 10) 118 #define CONFIG_ENV_SIZE (256 << 10) 119 #define CONFIG_ENV_OVERWRITE 120 121 /* Console settings */ 122 123 /* U-Boot memory settings */ 124 #define CONFIG_SYS_MALLOC_LEN (1 << 20) 125 126 #endif /* __CONFIG_H */ 127