1*b8d41ddaSRyan Mallon /* 2*b8d41ddaSRyan Mallon * Bluewater Systems Snapper 9260 and 9G20 modules 3*b8d41ddaSRyan Mallon * 4*b8d41ddaSRyan Mallon * (C) Copyright 2011 Bluewater Systems 5*b8d41ddaSRyan Mallon * Author: Andre Renaud <andre@bluewatersys.com> 6*b8d41ddaSRyan Mallon * Author: Ryan Mallon <ryan@bluewatersys.com> 7*b8d41ddaSRyan Mallon * 8*b8d41ddaSRyan Mallon * See file CREDITS for list of people who contributed to this 9*b8d41ddaSRyan Mallon * project. 10*b8d41ddaSRyan Mallon * 11*b8d41ddaSRyan Mallon * This program is free software; you can redistribute it and/or 12*b8d41ddaSRyan Mallon * modify it under the terms of the GNU General Public License as 13*b8d41ddaSRyan Mallon * published by the Free Software Foundation; either version 2 of 14*b8d41ddaSRyan Mallon * the License, or (at your option) any later version. 15*b8d41ddaSRyan Mallon * 16*b8d41ddaSRyan Mallon * This program is distributed in the hope that it will be useful, 17*b8d41ddaSRyan Mallon * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*b8d41ddaSRyan Mallon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*b8d41ddaSRyan Mallon * GNU General Public License for more details. 20*b8d41ddaSRyan Mallon * 21*b8d41ddaSRyan Mallon * You should have received a copy of the GNU General Public License 22*b8d41ddaSRyan Mallon * along with this program; if not, write to the Free Software 23*b8d41ddaSRyan Mallon * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*b8d41ddaSRyan Mallon * MA 02111-1307 USA 25*b8d41ddaSRyan Mallon */ 26*b8d41ddaSRyan Mallon 27*b8d41ddaSRyan Mallon #ifndef __CONFIG_H 28*b8d41ddaSRyan Mallon #define __CONFIG_H 29*b8d41ddaSRyan Mallon 30*b8d41ddaSRyan Mallon /* SoC type is defined in boards.cfg */ 31*b8d41ddaSRyan Mallon #include <asm/hardware.h> 32*b8d41ddaSRyan Mallon #include <asm/sizes.h> 33*b8d41ddaSRyan Mallon 34*b8d41ddaSRyan Mallon #define CONFIG_SYS_TEXT_BASE 0x20000000 35*b8d41ddaSRyan Mallon 36*b8d41ddaSRyan Mallon /* ARM asynchronous clock */ 37*b8d41ddaSRyan Mallon #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ 38*b8d41ddaSRyan Mallon #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 39*b8d41ddaSRyan Mallon #define CONFIG_SYS_HZ 1000 40*b8d41ddaSRyan Mallon 41*b8d41ddaSRyan Mallon /* CPU */ 42*b8d41ddaSRyan Mallon #define CONFIG_ARCH_CPU_INIT 43*b8d41ddaSRyan Mallon #undef CONFIG_USE_IRQ 44*b8d41ddaSRyan Mallon 45*b8d41ddaSRyan Mallon #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 46*b8d41ddaSRyan Mallon #define CONFIG_SETUP_MEMORY_TAGS 47*b8d41ddaSRyan Mallon #define CONFIG_INITRD_TAG 48*b8d41ddaSRyan Mallon #define CONFIG_SKIP_LOWLEVEL_INIT 49*b8d41ddaSRyan Mallon #define CONFIG_SKIP_RELOCATE_UBOOT 50*b8d41ddaSRyan Mallon #define CONFIG_DISPLAY_CPUINFO 51*b8d41ddaSRyan Mallon #define CONFIG_FIT 52*b8d41ddaSRyan Mallon 53*b8d41ddaSRyan Mallon /* SDRAM */ 54*b8d41ddaSRyan Mallon #define CONFIG_NR_DRAM_BANKS 1 55*b8d41ddaSRyan Mallon #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 56*b8d41ddaSRyan Mallon #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ 57*b8d41ddaSRyan Mallon #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ 58*b8d41ddaSRyan Mallon GENERATED_GBL_DATA_SIZE) 59*b8d41ddaSRyan Mallon 60*b8d41ddaSRyan Mallon /* Mem test settings */ 61*b8d41ddaSRyan Mallon #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 62*b8d41ddaSRyan Mallon #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) 63*b8d41ddaSRyan Mallon 64*b8d41ddaSRyan Mallon /* NAND Flash */ 65*b8d41ddaSRyan Mallon #define CONFIG_NAND_ATMEL 66*b8d41ddaSRyan Mallon #define CONFIG_SYS_NO_FLASH 67*b8d41ddaSRyan Mallon #define CONFIG_SYS_MAX_NAND_DEVICE 1 68*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 69*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_DBW_8 70*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ 71*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ 72*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 73*b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 74*b8d41ddaSRyan Mallon 75*b8d41ddaSRyan Mallon /* Ethernet */ 76*b8d41ddaSRyan Mallon #define CONFIG_MACB 77*b8d41ddaSRyan Mallon #define CONFIG_RMII 78*b8d41ddaSRyan Mallon #define CONFIG_NET_MULTI 79*b8d41ddaSRyan Mallon #define CONFIG_NET_RETRY_COUNT 20 80*b8d41ddaSRyan Mallon #define CONFIG_RESET_PHY_R 81*b8d41ddaSRyan Mallon #define CONFIG_TFTP_PORT 82*b8d41ddaSRyan Mallon #define CONFIG_TFTP_TSIZE 83*b8d41ddaSRyan Mallon 84*b8d41ddaSRyan Mallon /* USB */ 85*b8d41ddaSRyan Mallon #define CONFIG_USB_ATMEL 86*b8d41ddaSRyan Mallon #define CONFIG_USB_OHCI_NEW 87*b8d41ddaSRyan Mallon #define CONFIG_DOS_PARTITION 88*b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_CPU_INIT 89*b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE 90*b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" 91*b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 92*b8d41ddaSRyan Mallon #define CONFIG_USB_STORAGE 93*b8d41ddaSRyan Mallon 94*b8d41ddaSRyan Mallon /* GPIOs and IO expander */ 95*b8d41ddaSRyan Mallon #define CONFIG_AT91_LEGACY 96*b8d41ddaSRyan Mallon #define CONFIG_ATMEL_LEGACY 97*b8d41ddaSRyan Mallon #define CONFIG_AT91_GPIO 98*b8d41ddaSRyan Mallon #define CONFIG_AT91_GPIO_PULLUP 1 99*b8d41ddaSRyan Mallon #define CONFIG_PCA953X 100*b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 101*b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } 102*b8d41ddaSRyan Mallon 103*b8d41ddaSRyan Mallon /* UARTs/Serial console */ 104*b8d41ddaSRyan Mallon #define CONFIG_ATMEL_USART 105*b8d41ddaSRyan Mallon #define CONFIG_USART_BASE ATMEL_BASE_DBGU 106*b8d41ddaSRyan Mallon #define CONFIG_USART_ID ATMEL_ID_SYS 107*b8d41ddaSRyan Mallon #define CONFIG_BAUDRATE 115200 108*b8d41ddaSRyan Mallon #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 109*b8d41ddaSRyan Mallon #define CONFIG_SYS_PROMPT "Snapper> " 110*b8d41ddaSRyan Mallon 111*b8d41ddaSRyan Mallon /* I2C - Bit-bashed */ 112*b8d41ddaSRyan Mallon #define CONFIG_SOFT_I2C 113*b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_SPEED 100000 114*b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_SLAVE 0x7F 115*b8d41ddaSRyan Mallon #define CONFIG_SOFT_I2C_READ_REPEATED_START 116*b8d41ddaSRyan Mallon #define CONFIG_I2C_MULTI_BUS 117*b8d41ddaSRyan Mallon #define I2C_INIT do { \ 118*b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA23, 1); \ 119*b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA24, 1); \ 120*b8d41ddaSRyan Mallon at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 121*b8d41ddaSRyan Mallon at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 122*b8d41ddaSRyan Mallon } while (0) 123*b8d41ddaSRyan Mallon #define I2C_SOFT_DECLARATIONS 124*b8d41ddaSRyan Mallon #define I2C_ACTIVE 125*b8d41ddaSRyan Mallon #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); 126*b8d41ddaSRyan Mallon #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); 127*b8d41ddaSRyan Mallon #define I2C_SDA(bit) do { \ 128*b8d41ddaSRyan Mallon if (bit) { \ 129*b8d41ddaSRyan Mallon at91_set_gpio_input(AT91_PIN_PA23, 1); \ 130*b8d41ddaSRyan Mallon } else { \ 131*b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA23, 1); \ 132*b8d41ddaSRyan Mallon at91_set_gpio_value(AT91_PIN_PA23, bit); \ 133*b8d41ddaSRyan Mallon } \ 134*b8d41ddaSRyan Mallon } while (0) 135*b8d41ddaSRyan Mallon #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 136*b8d41ddaSRyan Mallon #define I2C_DELAY udelay(2) 137*b8d41ddaSRyan Mallon 138*b8d41ddaSRyan Mallon /* Boot options */ 139*b8d41ddaSRyan Mallon #define CONFIG_SYS_LOAD_ADDR 0x23000000 140*b8d41ddaSRyan Mallon #define CONFIG_BOOTDELAY 3 141*b8d41ddaSRyan Mallon #define CONFIG_ZERO_BOOTDELAY_CHECK 142*b8d41ddaSRyan Mallon 143*b8d41ddaSRyan Mallon #define CONFIG_BOOTP_BOOTFILESIZE 144*b8d41ddaSRyan Mallon #define CONFIG_BOOTP_BOOTPATH 145*b8d41ddaSRyan Mallon #define CONFIG_BOOTP_GATEWAY 146*b8d41ddaSRyan Mallon #define CONFIG_BOOTP_HOSTNAME 147*b8d41ddaSRyan Mallon 148*b8d41ddaSRyan Mallon /* Environment settings */ 149*b8d41ddaSRyan Mallon #define CONFIG_ENV_IS_IN_NAND 150*b8d41ddaSRyan Mallon #define CONFIG_ENV_OFFSET (512 << 10) 151*b8d41ddaSRyan Mallon #define CONFIG_ENV_SIZE (256 << 10) 152*b8d41ddaSRyan Mallon #define CONFIG_ENV_OVERWRITE 153*b8d41ddaSRyan Mallon #define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any" 154*b8d41ddaSRyan Mallon 155*b8d41ddaSRyan Mallon /* Console settings */ 156*b8d41ddaSRyan Mallon #define CONFIG_SYS_CBSIZE 256 157*b8d41ddaSRyan Mallon #define CONFIG_SYS_MAXARGS 16 158*b8d41ddaSRyan Mallon #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 159*b8d41ddaSRyan Mallon sizeof(CONFIG_SYS_PROMPT) + 16) 160*b8d41ddaSRyan Mallon #define CONFIG_SYS_LONGHELP 161*b8d41ddaSRyan Mallon #define CONFIG_SYS_EXTBDINFO 162*b8d41ddaSRyan Mallon #define CONFIG_CMDLINE_EDITING 163*b8d41ddaSRyan Mallon #define CONFIG_AUTO_COMPLETE 164*b8d41ddaSRyan Mallon #define CONFIG_SYS_HUSH_PARSER 165*b8d41ddaSRyan Mallon #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 166*b8d41ddaSRyan Mallon 167*b8d41ddaSRyan Mallon /* U-Boot memory settings */ 168*b8d41ddaSRyan Mallon #define CONFIG_SYS_MALLOC_LEN (1 << 20) 169*b8d41ddaSRyan Mallon #define CONFIG_STACKSIZE (256 << 10) 170*b8d41ddaSRyan Mallon 171*b8d41ddaSRyan Mallon /* Command line configuration */ 172*b8d41ddaSRyan Mallon #include <config_cmd_default.h> 173*b8d41ddaSRyan Mallon #undef CONFIG_CMD_BDI 174*b8d41ddaSRyan Mallon #undef CONFIG_CMD_FPGA 175*b8d41ddaSRyan Mallon #undef CONFIG_CMD_IMI 176*b8d41ddaSRyan Mallon #undef CONFIG_CMD_IMLS 177*b8d41ddaSRyan Mallon #undef CONFIG_CMD_LOADS 178*b8d41ddaSRyan Mallon #undef CONFIG_CMD_SOURCE 179*b8d41ddaSRyan Mallon 180*b8d41ddaSRyan Mallon #define CONFIG_CMD_PING 181*b8d41ddaSRyan Mallon #define CONFIG_CMD_DHCP 182*b8d41ddaSRyan Mallon #define CONFIG_CMD_FAT 183*b8d41ddaSRyan Mallon #define CONFIG_CMD_I2C 184*b8d41ddaSRyan Mallon #undef CONFIG_CMD_GPIO 185*b8d41ddaSRyan Mallon #define CONFIG_CMD_USB 186*b8d41ddaSRyan Mallon #define CONFIG_CMD_MII 187*b8d41ddaSRyan Mallon #define CONFIG_CMD_NAND 188*b8d41ddaSRyan Mallon #define CONFIG_CMD_PCA953X 189*b8d41ddaSRyan Mallon #define CONFIG_CMD_PCA953X_INFO 190*b8d41ddaSRyan Mallon 191*b8d41ddaSRyan Mallon #endif /* __CONFIG_H */ 192