1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b8d41ddaSRyan Mallon /* 3b8d41ddaSRyan Mallon * Bluewater Systems Snapper 9260 and 9G20 modules 4b8d41ddaSRyan Mallon * 5b8d41ddaSRyan Mallon * (C) Copyright 2011 Bluewater Systems 6b8d41ddaSRyan Mallon * Author: Andre Renaud <andre@bluewatersys.com> 7b8d41ddaSRyan Mallon * Author: Ryan Mallon <ryan@bluewatersys.com> 8b8d41ddaSRyan Mallon */ 9b8d41ddaSRyan Mallon 10b8d41ddaSRyan Mallon #ifndef __CONFIG_H 11b8d41ddaSRyan Mallon #define __CONFIG_H 12b8d41ddaSRyan Mallon 13b8d41ddaSRyan Mallon /* SoC type is defined in boards.cfg */ 14b8d41ddaSRyan Mallon #include <asm/hardware.h> 151ace4022SAlexey Brodkin #include <linux/sizes.h> 16b8d41ddaSRyan Mallon 17b8d41ddaSRyan Mallon /* ARM asynchronous clock */ 18b8d41ddaSRyan Mallon #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ 19b8d41ddaSRyan Mallon #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 20b8d41ddaSRyan Mallon 21b8d41ddaSRyan Mallon /* CPU */ 22b8d41ddaSRyan Mallon #define CONFIG_ARCH_CPU_INIT 23b8d41ddaSRyan Mallon 24b8d41ddaSRyan Mallon #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 25b8d41ddaSRyan Mallon #define CONFIG_SETUP_MEMORY_TAGS 26b8d41ddaSRyan Mallon #define CONFIG_INITRD_TAG 27b8d41ddaSRyan Mallon #define CONFIG_SKIP_LOWLEVEL_INIT 28b8d41ddaSRyan Mallon 29b8d41ddaSRyan Mallon /* SDRAM */ 30b8d41ddaSRyan Mallon #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 31b8d41ddaSRyan Mallon #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ 32b8d41ddaSRyan Mallon #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ 33b8d41ddaSRyan Mallon GENERATED_GBL_DATA_SIZE) 34b8d41ddaSRyan Mallon 35b8d41ddaSRyan Mallon /* Mem test settings */ 36b8d41ddaSRyan Mallon #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 37b8d41ddaSRyan Mallon #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) 38b8d41ddaSRyan Mallon 39b8d41ddaSRyan Mallon /* NAND Flash */ 40b8d41ddaSRyan Mallon #define CONFIG_SYS_MAX_NAND_DEVICE 1 41b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 42b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_DBW_8 43b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ 44b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ 45b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 46b8d41ddaSRyan Mallon #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 47b8d41ddaSRyan Mallon 48b8d41ddaSRyan Mallon /* Ethernet */ 49b8d41ddaSRyan Mallon #define CONFIG_MACB 50b8d41ddaSRyan Mallon #define CONFIG_RMII 51b8d41ddaSRyan Mallon #define CONFIG_NET_RETRY_COUNT 20 52b8d41ddaSRyan Mallon #define CONFIG_RESET_PHY_R 534535a24cSHeiko Schocher #define CONFIG_AT91_WANTS_COMMON_PHY 54b8d41ddaSRyan Mallon #define CONFIG_TFTP_PORT 55b8d41ddaSRyan Mallon #define CONFIG_TFTP_TSIZE 56b8d41ddaSRyan Mallon 57b8d41ddaSRyan Mallon /* USB */ 58b8d41ddaSRyan Mallon #define CONFIG_USB_ATMEL 59dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 60b8d41ddaSRyan Mallon #define CONFIG_USB_OHCI_NEW 61b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_CPU_INIT 62b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE 63b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" 64b8d41ddaSRyan Mallon #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 65b8d41ddaSRyan Mallon 66b8d41ddaSRyan Mallon /* GPIOs and IO expander */ 67b8d41ddaSRyan Mallon #define CONFIG_ATMEL_LEGACY 68b8d41ddaSRyan Mallon #define CONFIG_AT91_GPIO 69b8d41ddaSRyan Mallon #define CONFIG_AT91_GPIO_PULLUP 1 70b8d41ddaSRyan Mallon #define CONFIG_PCA953X 71b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 72b8d41ddaSRyan Mallon #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } 73b8d41ddaSRyan Mallon 74b8d41ddaSRyan Mallon /* UARTs/Serial console */ 75b8d41ddaSRyan Mallon #define CONFIG_ATMEL_USART 761a1927f3SSimon Glass #ifndef CONFIG_DM_SERIAL 77b8d41ddaSRyan Mallon #define CONFIG_USART_BASE ATMEL_BASE_DBGU 78b8d41ddaSRyan Mallon #define CONFIG_USART_ID ATMEL_ID_SYS 791a1927f3SSimon Glass #endif 80b8d41ddaSRyan Mallon 81b8d41ddaSRyan Mallon /* I2C - Bit-bashed */ 82ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C 83ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 84ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C_SOFT_SPEED 100000 85ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 86b8d41ddaSRyan Mallon #define CONFIG_SOFT_I2C_READ_REPEATED_START 87b8d41ddaSRyan Mallon #define I2C_INIT do { \ 88b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA23, 1); \ 89b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA24, 1); \ 90b8d41ddaSRyan Mallon at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 91b8d41ddaSRyan Mallon at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 92b8d41ddaSRyan Mallon } while (0) 93b8d41ddaSRyan Mallon #define I2C_SOFT_DECLARATIONS 94b8d41ddaSRyan Mallon #define I2C_ACTIVE 95b8d41ddaSRyan Mallon #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); 96b8d41ddaSRyan Mallon #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); 97b8d41ddaSRyan Mallon #define I2C_SDA(bit) do { \ 98b8d41ddaSRyan Mallon if (bit) { \ 99b8d41ddaSRyan Mallon at91_set_gpio_input(AT91_PIN_PA23, 1); \ 100b8d41ddaSRyan Mallon } else { \ 101b8d41ddaSRyan Mallon at91_set_gpio_output(AT91_PIN_PA23, 1); \ 102b8d41ddaSRyan Mallon at91_set_gpio_value(AT91_PIN_PA23, bit); \ 103b8d41ddaSRyan Mallon } \ 104b8d41ddaSRyan Mallon } while (0) 105b8d41ddaSRyan Mallon #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 106b8d41ddaSRyan Mallon #define I2C_DELAY udelay(2) 107b8d41ddaSRyan Mallon 108b8d41ddaSRyan Mallon /* Boot options */ 109b8d41ddaSRyan Mallon #define CONFIG_SYS_LOAD_ADDR 0x23000000 110b8d41ddaSRyan Mallon 111b8d41ddaSRyan Mallon #define CONFIG_BOOTP_BOOTFILESIZE 112b8d41ddaSRyan Mallon 113b8d41ddaSRyan Mallon /* Environment settings */ 114b8d41ddaSRyan Mallon #define CONFIG_ENV_OFFSET (512 << 10) 115b8d41ddaSRyan Mallon #define CONFIG_ENV_SIZE (256 << 10) 116b8d41ddaSRyan Mallon #define CONFIG_ENV_OVERWRITE 117b8d41ddaSRyan Mallon 118b8d41ddaSRyan Mallon /* Console settings */ 119b8d41ddaSRyan Mallon 120b8d41ddaSRyan Mallon /* U-Boot memory settings */ 121b8d41ddaSRyan Mallon #define CONFIG_SYS_MALLOC_LEN (1 << 20) 122b8d41ddaSRyan Mallon 123b8d41ddaSRyan Mallon #endif /* __CONFIG_H */ 124