1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * 4 * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 30 #define CONFIG_S5P /* S5P Family */ 31 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ 32 #define CONFIG_SMDK5250 /* which is in a SMDK5250 */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 36 #define CONFIG_ARCH_CPU_INIT 37 #define CONFIG_DISPLAY_CPUINFO 38 #define CONFIG_DISPLAY_BOARDINFO 39 40 /* Keep L2 Cache Disabled */ 41 #define CONFIG_SYS_DCACHE_OFF 42 43 #define CONFIG_SYS_SDRAM_BASE 0x40000000 44 #define CONFIG_SYS_TEXT_BASE 0x43E00000 45 46 /* input clock of PLL: SMDK5250 has 24MHz input clock */ 47 #define CONFIG_SYS_CLK_FREQ 24000000 48 49 #define CONFIG_SETUP_MEMORY_TAGS 50 #define CONFIG_CMDLINE_TAG 51 #define CONFIG_INITRD_TAG 52 #define CONFIG_CMDLINE_EDITING 53 54 /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ 55 #define MACH_TYPE_SMDK5250 3774 56 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 57 58 /* Power Down Modes */ 59 #define S5P_CHECK_SLEEP 0x00000BAD 60 #define S5P_CHECK_DIDLE 0xBAD00000 61 #define S5P_CHECK_LPA 0xABAD0000 62 63 /* Offset for inform registers */ 64 #define INFORM0_OFFSET 0x800 65 #define INFORM1_OFFSET 0x804 66 67 /* Size of malloc() pool */ 68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) 69 70 /* select serial console configuration */ 71 #define CONFIG_SERIAL3 /* use SERIAL 3 */ 72 #define CONFIG_BAUDRATE 115200 73 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 74 75 #define TZPC_BASE_OFFSET 0x10000 76 77 /* SD/MMC configuration */ 78 #define CONFIG_GENERIC_MMC 79 #define CONFIG_MMC 80 #define CONFIG_SDHCI 81 #define CONFIG_S5P_SDHCI 82 83 #define CONFIG_BOARD_EARLY_INIT_F 84 85 /* PWM */ 86 #define CONFIG_PWM 87 88 /* allow to overwrite serial and ethaddr */ 89 #define CONFIG_ENV_OVERWRITE 90 91 /* Command definition*/ 92 #include <config_cmd_default.h> 93 94 #define CONFIG_CMD_PING 95 #define CONFIG_CMD_ELF 96 #define CONFIG_CMD_MMC 97 #define CONFIG_CMD_EXT2 98 #define CONFIG_CMD_FAT 99 #define CONFIG_CMD_NET 100 101 #define CONFIG_BOOTDELAY 3 102 #define CONFIG_ZERO_BOOTDELAY_CHECK 103 104 /* USB */ 105 #define CONFIG_CMD_USB 106 #define CONFIG_USB_EHCI 107 #define CONFIG_USB_EHCI_EXYNOS 108 #define CONFIG_USB_STORAGE 109 110 /* MMC SPL */ 111 #define CONFIG_SPL 112 #define COPY_BL2_FNPTR_ADDR 0x02020030 113 114 /* specific .lds file */ 115 #define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds" 116 #define CONFIG_SPL_TEXT_BASE 0x02023400 117 #define CONFIG_SPL_MAX_SIZE (14 * 1024) 118 119 #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" 120 121 /* Miscellaneous configurable options */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 124 #define CONFIG_SYS_PROMPT "SMDK5250 # " 125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 126 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ 127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 128 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" 129 /* Boot Argument Buffer Size */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 131 /* memtest works on */ 132 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 133 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 134 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 135 136 #define CONFIG_SYS_HZ 1000 137 138 #define CONFIG_RD_LVL 139 140 #define CONFIG_NR_DRAM_BANKS 8 141 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ 142 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 143 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 144 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 145 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 146 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 147 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 148 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 149 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 150 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 151 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 152 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 153 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 154 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 155 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 156 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 157 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 158 159 #define CONFIG_SYS_MONITOR_BASE 0x00000000 160 161 /* FLASH and environment organization */ 162 #define CONFIG_SYS_NO_FLASH 163 #undef CONFIG_CMD_IMLS 164 #define CONFIG_IDENT_STRING " for SMDK5250" 165 166 #define CONFIG_SYS_MMC_ENV_DEV 0 167 168 #define CONFIG_SECURE_BL1_ONLY 169 170 /* Secure FW size configuration */ 171 #ifdef CONFIG_SECURE_BL1_ONLY 172 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 173 #else 174 #define CONFIG_SEC_FW_SIZE 0 175 #endif 176 177 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 178 #define CONFIG_RES_BLOCK_SIZE (512) 179 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 180 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 181 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 182 183 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 184 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 185 #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) 186 187 /* U-boot copy size from boot Media to DRAM.*/ 188 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 189 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 190 191 #define OM_STAT (0x1f << 1) 192 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 193 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) 194 195 #define CONFIG_DOS_PARTITION 196 197 #define CONFIG_IRAM_STACK 0x02050000 198 199 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) 200 201 /* I2C */ 202 #define CONFIG_SYS_I2C_INIT_BOARD 203 #define CONFIG_HARD_I2C 204 #define CONFIG_CMD_I2C 205 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ 206 #define CONFIG_DRIVER_S3C24X0_I2C 207 #define CONFIG_I2C_MULTI_BUS 208 #define CONFIG_MAX_I2C_NUM 8 209 #define CONFIG_SYS_I2C_SLAVE 0x0 210 #define CONFIG_I2C_EDID 211 212 /* PMIC */ 213 #define CONFIG_PMIC 214 #define CONFIG_PMIC_I2C 215 #define CONFIG_PMIC_MAX77686 216 217 /* SPI */ 218 #define CONFIG_ENV_IS_IN_SPI_FLASH 219 #define CONFIG_SPI_FLASH 220 221 #ifdef CONFIG_SPI_FLASH 222 #define CONFIG_EXYNOS_SPI 223 #define CONFIG_CMD_SF 224 #define CONFIG_CMD_SPI 225 #define CONFIG_SPI_FLASH_WINBOND 226 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 227 #define CONFIG_SF_DEFAULT_SPEED 50000000 228 #define EXYNOS5_SPI_NUM_CONTROLLERS 5 229 #endif 230 231 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 232 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 233 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 234 #define CONFIG_ENV_SPI_BUS 1 235 #define CONFIG_ENV_SPI_MAX_HZ 50000000 236 #endif 237 238 /* PMIC */ 239 #define CONFIG_POWER 240 #define CONFIG_POWER_I2C 241 #define CONFIG_POWER_MAX77686 242 243 /* SPI */ 244 #define CONFIG_ENV_IS_IN_SPI_FLASH 245 #define CONFIG_SPI_FLASH 246 247 #ifdef CONFIG_SPI_FLASH 248 #define CONFIG_EXYNOS_SPI 249 #define CONFIG_CMD_SF 250 #define CONFIG_CMD_SPI 251 #define CONFIG_SPI_FLASH_WINBOND 252 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 253 #define CONFIG_SF_DEFAULT_SPEED 50000000 254 #define EXYNOS5_SPI_NUM_CONTROLLERS 5 255 #endif 256 257 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 258 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 259 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 260 #define CONFIG_ENV_SPI_BUS 1 261 #define CONFIG_ENV_SPI_MAX_HZ 50000000 262 #endif 263 264 /* Ethernet Controllor Driver */ 265 #ifdef CONFIG_CMD_NET 266 #define CONFIG_SMC911X 267 #define CONFIG_SMC911X_BASE 0x5000000 268 #define CONFIG_SMC911X_16_BIT 269 #define CONFIG_ENV_SROM_BANK 1 270 #endif /*CONFIG_CMD_NET*/ 271 272 /* Enable PXE Support */ 273 #ifdef CONFIG_CMD_NET 274 #define CONFIG_CMD_PXE 275 #define CONFIG_MENU 276 #endif 277 278 /* Sound */ 279 #define CONFIG_CMD_SOUND 280 #ifdef CONFIG_CMD_SOUND 281 #define CONFIG_SOUND 282 #define CONFIG_I2S 283 #define CONFIG_SOUND_WM8994 284 #endif 285 286 /* Enable devicetree support */ 287 #define CONFIG_OF_LIBFDT 288 289 /* SHA hashing */ 290 #define CONFIG_CMD_HASH 291 #define CONFIG_HASH_VERIFY 292 #define CONFIG_SHA1 293 #define CONFIG_SHA256 294 295 #endif /* __CONFIG_H */ 296