xref: /openbmc/u-boot/include/configs/smartweb.h (revision cd1cc31f)
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * (C) Copyright 2010
7  * Achim Ehrlich <aehrlich@taskit.de>
8  * taskit GmbH <www.taskit.de>
9  *
10  * (C) Copyright 2012
11  * Markus Hubig <mhubig@imko.de>
12  * IMKO GmbH <www.imko.de>
13  *
14  * (C) Copyright 2014
15  * Heiko Schocher <hs@denx.de>
16  * DENX Software Engineering GmbH
17  *
18  * Configuation settings for the smartweb.
19  *
20  * SPDX-License-Identifier:	GPL-2.0+
21  */
22 
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25 
26 /*
27  * SoC must be defined first, before hardware.h is included.
28  * In this case SoC is defined in boards.cfg.
29  */
30 #include <asm/hardware.h>
31 #include <linux/sizes.h>
32 
33 /*
34  * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
35  * program. Since the linker has to swallow that define, we must use a pure
36  * hex number here!
37  */
38 #define CONFIG_SYS_TEXT_BASE		0x23000000
39 
40 /* ARM asynchronous clock */
41 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
42 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
43 
44 /* misc settings */
45 #define CONFIG_CMDLINE_TAG		/* pass commandline to Kernel */
46 #define CONFIG_SETUP_MEMORY_TAGS	/* pass memory defs to kernel */
47 #define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
48 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY	/* U-Boot is loaded by a bootloader */
49 
50 /* We set the max number of command args high to avoid HUSH bugs. */
51 #define CONFIG_SYS_MAXARGS    32
52 
53 /* setting board specific options */
54 #define CONFIG_MACH_TYPE		MACH_TYPE_SMARTWEB
55 #define CONFIG_AUTO_COMPLETE
56 #define CONFIG_ENV_OVERWRITE    1 /* Overwrite ethaddr / serial# */
57 #define CONFIG_AUTO_COMPLETE
58 #define CONFIG_SYS_AUTOLOAD "yes"
59 #define CONFIG_RESET_TO_RETRY
60 
61 /* The LED PINs */
62 #define CONFIG_RED_LED			AT91_PIN_PA9
63 #define CONFIG_GREEN_LED		AT91_PIN_PA6
64 
65 /*
66  * SDRAM: 1 bank, 64 MB, base address 0x20000000
67  * Already initialized before u-boot gets started.
68  */
69 #define CONFIG_NR_DRAM_BANKS		1
70 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
71 #define CONFIG_SYS_SDRAM_SIZE		(64 * SZ_1M)
72 
73 /*
74  * Perform a SDRAM Memtest from the start of SDRAM
75  * till the beginning of the U-Boot position in RAM.
76  */
77 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
78 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
79 
80 /* Size of malloc() pool */
81 #define CONFIG_SYS_MALLOC_LEN \
82 	ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000)
83 
84 /* NAND flash settings */
85 #define CONFIG_NAND_ATMEL
86 #define CONFIG_SYS_MAX_NAND_DEVICE	1
87 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
88 #define CONFIG_SYS_NAND_DBW_8
89 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
90 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
91 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
92 #define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
93 
94 #define CONFIG_MTD_DEVICE
95 
96 /* general purpose I/O */
97 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
98 #define CONFIG_AT91_GPIO		/* enable the GPIO features */
99 #define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
100 
101 /* serial console */
102 #define CONFIG_ATMEL_USART
103 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
104 #define CONFIG_USART_ID			ATMEL_ID_SYS
105 
106 /*
107  * Ethernet configuration
108  *
109  */
110 #define CONFIG_MACB
111 #define CONFIG_RMII			/* use reduced MII inteface */
112 #define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
113 #define CONFIG_AT91_WANTS_COMMON_PHY
114 
115 /* BOOTP and DHCP options */
116 #define CONFIG_BOOTP_BOOTFILESIZE
117 #define CONFIG_BOOTP_BOOTPATH
118 #define CONFIG_BOOTP_GATEWAY
119 #define CONFIG_BOOTP_HOSTNAME
120 #define CONFIG_NFSBOOTCOMMAND						\
121 	"setenv autoload yes; setenv autoboot yes; "			\
122 	"setenv bootargs ${basicargs} ${mtdparts} "			\
123 	"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; "	\
124 	"dhcp"
125 
126 /* Enable the watchdog */
127 #define CONFIG_AT91SAM9_WATCHDOG
128 #if !defined(CONFIG_SPL_BUILD)
129 #define CONFIG_HW_WATCHDOG
130 #endif
131 #define CONFIG_AT91_HW_WDT_TIMEOUT	15
132 
133 #if !defined(CONFIG_SPL_BUILD)
134 /* USB configuration */
135 #define CONFIG_USB_ATMEL
136 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
137 #define CONFIG_USB_OHCI_NEW
138 #define CONFIG_SYS_USB_OHCI_CPU_INIT
139 #define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
140 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
141 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
142 
143 /* USB DFU support */
144 #define CONFIG_MTD_DEVICE
145 #define CONFIG_MTD_PARTITIONS
146 
147 #define CONFIG_USB_GADGET_AT91
148 
149 /* DFU class support */
150 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
151 #define DFU_MANIFEST_POLL_TIMEOUT	25000
152 #endif
153 
154 /* General Boot Parameter */
155 #define CONFIG_BOOTCOMMAND		"run flashboot"
156 #define CONFIG_SYS_CBSIZE		512
157 #define CONFIG_SYS_LONGHELP
158 #define CONFIG_CMDLINE_EDITING
159 
160 /*
161  * RAM Memory address where to put the
162  * Linux Kernel befor starting.
163  */
164 #define CONFIG_SYS_LOAD_ADDR		0x22000000
165 
166 /*
167  * The NAND Flash partitions:
168  */
169 #define CONFIG_ENV_OFFSET		(0x100000)
170 #define CONFIG_ENV_OFFSET_REDUND	(0x180000)
171 #define CONFIG_ENV_RANGE		(SZ_512K)
172 #define CONFIG_ENV_SIZE			(SZ_128K)
173 
174 /*
175  * Predefined environment variables.
176  * Usefull to define some easy to use boot commands.
177  */
178 #define	CONFIG_EXTRA_ENV_SETTINGS					\
179 									\
180 	"basicargs=console=ttyS0,115200\0"				\
181 									\
182 	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
183 
184 #ifdef CONFIG_SPL_BUILD
185 #define CONFIG_SYS_INIT_SP_ADDR		0x301000
186 #define CONFIG_SPL_STACK_R
187 #define CONFIG_SPL_STACK_R_ADDR		CONFIG_SYS_TEXT_BASE
188 #else
189 /*
190  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
191  * leaving the correct space for initial global data structure above that
192  * address while providing maximum stack area below.
193  */
194 #define CONFIG_SYS_INIT_SP_ADDR \
195 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
196 #endif
197 
198 /* Defines for SPL */
199 #define CONFIG_SPL_FRAMEWORK
200 #define CONFIG_SPL_TEXT_BASE		0x0
201 #define CONFIG_SPL_MAX_SIZE		(SZ_4K)
202 
203 #define CONFIG_SPL_BSS_START_ADDR	CONFIG_SYS_SDRAM_BASE
204 #define CONFIG_SPL_BSS_MAX_SIZE		(SZ_16K)
205 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
206 					CONFIG_SPL_BSS_MAX_SIZE)
207 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
208 
209 #define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
210 #define CONFIG_SYS_USE_NANDFLASH	1
211 #define CONFIG_SPL_NAND_DRIVERS
212 #define CONFIG_SPL_NAND_BASE
213 #define CONFIG_SPL_NAND_ECC
214 #define CONFIG_SPL_NAND_RAW_ONLY
215 #define CONFIG_SPL_NAND_SOFTECC
216 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
217 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
218 #define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
219 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
220 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
221 
222 #define CONFIG_SYS_NAND_SIZE		(SZ_256M)
223 #define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
224 #define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
225 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
226 					 CONFIG_SYS_NAND_PAGE_SIZE)
227 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
228 #define CONFIG_SYS_NAND_ECCSIZE		256
229 #define CONFIG_SYS_NAND_ECCBYTES	3
230 #define CONFIG_SYS_NAND_OOBSIZE		64
231 #define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
232 					  48, 49, 50, 51, 52, 53, 54, 55, \
233 					  56, 57, 58, 59, 60, 61, 62, 63, }
234 
235 #define CONFIG_SPL_ATMEL_SIZE
236 #define CONFIG_SYS_MASTER_CLOCK		(198656000/2)
237 #define AT91_PLL_LOCK_TIMEOUT		1000000
238 #define CONFIG_SYS_AT91_PLLA		0x2060bf09
239 #define CONFIG_SYS_MCKR			0x100
240 #define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
241 #define CONFIG_SYS_AT91_PLLB		0x10483f0e
242 
243 #if defined(CONFIG_SPL_BUILD)
244 #define CONFIG_SYS_ICACHE_OFF
245 #define CONFIG_SYS_DCACHE_OFF
246 #endif
247 #endif /* __CONFIG_H */
248