1 /* 2 * include/configs/silk.h 3 * This file is silk board configuration. 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 * Copyright (C) 2015 Cogent Embedded, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __SILK_H 12 #define __SILK_H 13 14 #undef DEBUG 15 #define CONFIG_R8A7794 16 #define CONFIG_RMOBILE_BOARD_STRING "Silk" 17 18 #include "rcar-gen2-common.h" 19 20 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 21 #define CONFIG_SYS_TEXT_BASE 0x70000000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0xE6304000 24 #endif 25 26 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 27 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 28 #else 29 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 30 #endif 31 #define STACK_AREA_SIZE 0xC000 32 #define LOW_LEVEL_MERAM_STACK \ 33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34 35 /* MEMORY */ 36 #define RCAR_GEN2_SDRAM_BASE 0x40000000 37 #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39 40 /* SCIF */ 41 #define CONFIG_SCIF_CONSOLE 42 #define CONFIG_CONS_SCIF2 43 #define CONFIG_SCIF_USE_EXT_CLK 44 45 /* FLASH */ 46 #define CONFIG_SPI 47 #define CONFIG_SPI_FLASH_BAR 48 #define CONFIG_SH_QSPI 49 #define CONFIG_SPI_FLASH 50 #define CONFIG_SPI_FLASH_SPANSION 51 #define CONFIG_SPI_FLASH_QUAD 52 #define CONFIG_SYS_NO_FLASH 53 54 /* SH Ether */ 55 #define CONFIG_NET_MULTI 56 #define CONFIG_SH_ETHER 57 #define CONFIG_SH_ETHER_USE_PORT 0 58 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 59 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 60 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 61 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 62 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 63 #define CONFIG_PHYLIB 64 #define CONFIG_PHY_MICREL 65 #define CONFIG_BITBANGMII 66 #define CONFIG_BITBANGMII_MULTI 67 68 /* Board Clock */ 69 #define RMOBILE_XTAL_CLK 20000000u 70 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 71 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 72 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 73 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 74 #define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ 75 76 #define CONFIG_SYS_TMU_CLK_DIV 4 77 78 /* i2c */ 79 #define CONFIG_CMD_I2C 80 #define CONFIG_SYS_I2C 81 #define CONFIG_SYS_I2C_SH 82 #define CONFIG_SYS_I2C_SLAVE 0x7F 83 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 84 #define CONFIG_SYS_I2C_SH_SPEED0 400000 85 #define CONFIG_SYS_I2C_SH_SPEED1 400000 86 #define CONFIG_SYS_I2C_SH_SPEED2 400000 87 #define CONFIG_SH_I2C_DATA_HIGH 4 88 #define CONFIG_SH_I2C_DATA_LOW 5 89 #define CONFIG_SH_I2C_CLOCK 10000000 90 91 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 92 93 /* USB */ 94 #define CONFIG_USB_STORAGE 95 #define CONFIG_USB_EHCI 96 #define CONFIG_USB_EHCI_RMOBILE 97 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 98 99 /* MMCIF */ 100 #define CONFIG_MMC 101 #define CONFIG_GENERIC_MMC 102 #define CONFIG_CMD_MMC 103 #define CONFIG_SH_MMCIF 104 #define CONFIG_SH_MMCIF_ADDR 0xee200000 105 #define CONFIG_SH_MMCIF_CLK 48000000 106 107 /* Module stop status bits */ 108 /* INTC-RT */ 109 #define CONFIG_SMSTP0_ENA 0x00400000 110 /* MSIF */ 111 #define CONFIG_SMSTP2_ENA 0x00002000 112 /* INTC-SYS, IRQC */ 113 #define CONFIG_SMSTP4_ENA 0x00000180 114 /* SCIF2 */ 115 #define CONFIG_SMSTP7_ENA 0x00080000 116 117 #endif /* __SILK_H */ 118