1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7785 1 14 #define CONFIG_SH7785LCR 1 15 16 #define CONFIG_CMD_PCI 17 #define CONFIG_CMD_SDRAM 18 #define CONFIG_CMD_SH_ZIMAGEBOOT 19 20 #define CONFIG_USB_STORAGE 21 #define CONFIG_DOS_PARTITION 22 #define CONFIG_MAC_PARTITION 23 24 #define CONFIG_BAUDRATE 115200 25 #define CONFIG_BOOTDELAY 3 26 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 27 28 #define CONFIG_EXTRA_ENV_SETTINGS \ 29 "bootdevice=0:1\0" \ 30 "usbload=usb reset;usbboot;usb stop;bootm\0" 31 32 #define CONFIG_VERSION_VARIABLE 33 #undef CONFIG_SHOW_BOOT_PROGRESS 34 35 /* MEMORY */ 36 #if defined(CONFIG_SH_32BIT) 37 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 38 /* 0x40000000 - 0x47FFFFFF does not use */ 39 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 40 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 41 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 42 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 43 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 44 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 45 #define SH7785LCR_USB_BASE (0xa6000000) 46 #else 47 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 48 #define SH7785LCR_SDRAM_BASE (0x08000000) 49 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 50 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 51 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 52 #define SH7785LCR_USB_BASE (0xb4000000) 53 #endif 54 55 #define CONFIG_SYS_LONGHELP 56 #define CONFIG_SYS_CBSIZE 256 57 #define CONFIG_SYS_PBSIZE 256 58 #define CONFIG_SYS_MAXARGS 16 59 #define CONFIG_SYS_BARGSIZE 512 60 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 61 62 /* SCIF */ 63 #define CONFIG_SCIF_CONSOLE 1 64 #define CONFIG_CONS_SCIF1 1 65 #define CONFIG_SCIF_EXT_CLOCK 1 66 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 67 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 68 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 69 70 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 71 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 72 (SH7785LCR_SDRAM_SIZE) - \ 73 4 * 1024 * 1024) 74 #undef CONFIG_SYS_ALT_MEMTEST 75 #undef CONFIG_SYS_MEMTEST_SCRATCH 76 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 77 78 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 79 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 80 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 81 82 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 83 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 84 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 85 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 86 87 /* FLASH */ 88 #define CONFIG_FLASH_CFI_DRIVER 89 #define CONFIG_SYS_FLASH_CFI 90 #undef CONFIG_SYS_FLASH_QUIET_TEST 91 #define CONFIG_SYS_FLASH_EMPTY_INFO 92 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 93 #define CONFIG_SYS_MAX_FLASH_SECT 512 94 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 96 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 97 (0 * SH7785LCR_FLASH_BANK_SIZE) } 98 99 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 100 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 101 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 102 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 103 104 #undef CONFIG_SYS_FLASH_PROTECTION 105 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 106 107 /* R8A66597 */ 108 #define CONFIG_USB_R8A66597_HCD 109 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 110 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 111 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 112 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 113 114 /* PCI Controller */ 115 #define CONFIG_PCI 116 #define CONFIG_SH4_PCI 117 #define CONFIG_SH7780_PCI 118 #if defined(CONFIG_SH_32BIT) 119 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 120 #define CONFIG_SH7780_PCI_LAR 0x5f000000 121 #define CONFIG_SH7780_PCI_BAR 0x5f000000 122 #else 123 #define CONFIG_SH7780_PCI_LSR 0x07f00001 124 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 125 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 126 #endif 127 #define CONFIG_PCI_PNP 128 #define CONFIG_PCI_SCAN_SHOW 1 129 130 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 131 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 132 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 133 134 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 135 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 136 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 137 138 #if defined(CONFIG_SH_32BIT) 139 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 140 #else 141 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 142 #endif 143 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 144 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 145 146 /* ENV setting */ 147 #define CONFIG_ENV_IS_IN_FLASH 148 #define CONFIG_ENV_OVERWRITE 1 149 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 150 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 151 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 152 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 153 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 154 155 /* Board Clock */ 156 /* The SCIF used external clock. system clock only used timer. */ 157 #define CONFIG_SYS_CLK_FREQ 50000000 158 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 159 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 160 #define CONFIG_SYS_TMU_CLK_DIV 4 161 162 #endif /* __SH7785LCR_H */ 163