1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7785 1 14 #define CONFIG_SH7785LCR 1 15 16 #define CONFIG_CMD_FLASH 17 #define CONFIG_CMD_MEMORY 18 #define CONFIG_CMD_PCI 19 #define CONFIG_CMD_PING 20 #define CONFIG_CMD_NFS 21 #define CONFIG_CMD_SDRAM 22 #define CONFIG_CMD_RUN 23 #define CONFIG_CMD_SAVEENV 24 #define CONFIG_CMD_SH_ZIMAGEBOOT 25 26 #define CONFIG_CMD_USB 27 #define CONFIG_USB_STORAGE 28 #define CONFIG_CMD_EXT2 29 #define CONFIG_CMD_FAT 30 #define CONFIG_DOS_PARTITION 31 #define CONFIG_MAC_PARTITION 32 33 #define CONFIG_BAUDRATE 115200 34 #define CONFIG_BOOTDELAY 3 35 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 36 37 #define CONFIG_EXTRA_ENV_SETTINGS \ 38 "bootdevice=0:1\0" \ 39 "usbload=usb reset;usbboot;usb stop;bootm\0" 40 41 #define CONFIG_VERSION_VARIABLE 42 #undef CONFIG_SHOW_BOOT_PROGRESS 43 44 /* MEMORY */ 45 #if defined(CONFIG_SH_32BIT) 46 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 47 /* 0x40000000 - 0x47FFFFFF does not use */ 48 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 49 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 50 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 51 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 52 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 53 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 54 #define SH7785LCR_USB_BASE (0xa6000000) 55 #else 56 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 57 #define SH7785LCR_SDRAM_BASE (0x08000000) 58 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 59 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 60 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 61 #define SH7785LCR_USB_BASE (0xb4000000) 62 #endif 63 64 #define CONFIG_SYS_LONGHELP 65 #define CONFIG_SYS_CBSIZE 256 66 #define CONFIG_SYS_PBSIZE 256 67 #define CONFIG_SYS_MAXARGS 16 68 #define CONFIG_SYS_BARGSIZE 512 69 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 70 71 /* SCIF */ 72 #define CONFIG_SCIF_CONSOLE 1 73 #define CONFIG_CONS_SCIF1 1 74 #define CONFIG_SCIF_EXT_CLOCK 1 75 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 76 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 77 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 78 79 80 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 81 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 82 (SH7785LCR_SDRAM_SIZE) - \ 83 4 * 1024 * 1024) 84 #undef CONFIG_SYS_ALT_MEMTEST 85 #undef CONFIG_SYS_MEMTEST_SCRATCH 86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 87 88 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 89 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 90 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 91 92 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 93 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 94 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 95 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 96 97 /* FLASH */ 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 #undef CONFIG_SYS_FLASH_QUIET_TEST 101 #define CONFIG_SYS_FLASH_EMPTY_INFO 102 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 103 #define CONFIG_SYS_MAX_FLASH_SECT 512 104 105 #define CONFIG_SYS_MAX_FLASH_BANKS 1 106 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 107 (0 * SH7785LCR_FLASH_BANK_SIZE) } 108 109 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 110 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 111 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 112 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 113 114 #undef CONFIG_SYS_FLASH_PROTECTION 115 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 116 117 /* R8A66597 */ 118 #define CONFIG_USB_R8A66597_HCD 119 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 120 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 121 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 122 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 123 124 /* PCI Controller */ 125 #define CONFIG_PCI 126 #define CONFIG_SH4_PCI 127 #define CONFIG_SH7780_PCI 128 #if defined(CONFIG_SH_32BIT) 129 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 130 #define CONFIG_SH7780_PCI_LAR 0x5f000000 131 #define CONFIG_SH7780_PCI_BAR 0x5f000000 132 #else 133 #define CONFIG_SH7780_PCI_LSR 0x07f00001 134 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 135 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 136 #endif 137 #define CONFIG_PCI_PNP 138 #define CONFIG_PCI_SCAN_SHOW 1 139 140 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 141 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 142 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 143 144 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 145 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 146 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 147 148 #if defined(CONFIG_SH_32BIT) 149 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 150 #else 151 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 152 #endif 153 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 154 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 155 156 /* Network device (RTL8169) support */ 157 #define CONFIG_RTL8169 158 159 /* ENV setting */ 160 #define CONFIG_ENV_IS_IN_FLASH 161 #define CONFIG_ENV_OVERWRITE 1 162 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 163 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 164 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 165 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 166 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 167 168 /* Board Clock */ 169 /* The SCIF used external clock. system clock only used timer. */ 170 #define CONFIG_SYS_CLK_FREQ 50000000 171 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 172 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 173 #define CONFIG_SYS_TMU_CLK_DIV 4 174 175 #endif /* __SH7785LCR_H */ 176