1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #define CONFIG_CPU_SH7785 1 13 14 #define CONFIG_EXTRA_ENV_SETTINGS \ 15 "bootdevice=0:1\0" \ 16 "usbload=usb reset;usbboot;usb stop;bootm\0" 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 #undef CONFIG_SHOW_BOOT_PROGRESS 20 21 /* MEMORY */ 22 #if defined(CONFIG_SH_32BIT) 23 /* 0x40000000 - 0x47FFFFFF does not use */ 24 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 25 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 26 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 27 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 28 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 29 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 30 #define SH7785LCR_USB_BASE (0xa6000000) 31 #else 32 #define SH7785LCR_SDRAM_BASE (0x08000000) 33 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 34 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 35 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 36 #define SH7785LCR_USB_BASE (0xb4000000) 37 #endif 38 39 #define CONFIG_SYS_PBSIZE 256 40 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 41 42 /* SCIF */ 43 #define CONFIG_CONS_SCIF1 1 44 #define CONFIG_SCIF_EXT_CLOCK 1 45 46 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 47 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 48 (SH7785LCR_SDRAM_SIZE) - \ 49 4 * 1024 * 1024) 50 #undef CONFIG_SYS_MEMTEST_SCRATCH 51 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 52 53 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 54 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 55 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 56 57 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 58 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 59 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 60 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 61 62 /* FLASH */ 63 #define CONFIG_FLASH_CFI_DRIVER 64 #define CONFIG_SYS_FLASH_CFI 65 #undef CONFIG_SYS_FLASH_QUIET_TEST 66 #define CONFIG_SYS_FLASH_EMPTY_INFO 67 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 68 #define CONFIG_SYS_MAX_FLASH_SECT 512 69 70 #define CONFIG_SYS_MAX_FLASH_BANKS 1 71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 72 (0 * SH7785LCR_FLASH_BANK_SIZE) } 73 74 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 75 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 76 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 77 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 78 79 #undef CONFIG_SYS_FLASH_PROTECTION 80 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 81 82 /* R8A66597 */ 83 #define CONFIG_USB_R8A66597_HCD 84 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 85 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 86 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 87 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 88 89 /* PCI Controller */ 90 #define CONFIG_SH4_PCI 91 #define CONFIG_SH7780_PCI 92 #if defined(CONFIG_SH_32BIT) 93 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 94 #define CONFIG_SH7780_PCI_LAR 0x5f000000 95 #define CONFIG_SH7780_PCI_BAR 0x5f000000 96 #else 97 #define CONFIG_SH7780_PCI_LSR 0x07f00001 98 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 99 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 100 #endif 101 #define CONFIG_PCI_SCAN_SHOW 1 102 103 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 104 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 105 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 106 107 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 108 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 109 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 110 111 #if defined(CONFIG_SH_32BIT) 112 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 113 #else 114 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 115 #endif 116 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 117 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 118 119 /* ENV setting */ 120 #define CONFIG_ENV_OVERWRITE 1 121 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 122 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 123 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 124 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 125 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 126 127 /* Board Clock */ 128 /* The SCIF used external clock. system clock only used timer. */ 129 #define CONFIG_SYS_CLK_FREQ 50000000 130 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 131 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 132 #define CONFIG_SYS_TMU_CLK_DIV 4 133 134 #endif /* __SH7785LCR_H */ 135