1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #define CONFIG_CPU_SH7785 1 13 #define CONFIG_SH7785LCR 1 14 15 #define CONFIG_CMD_PCI 16 #define CONFIG_CMD_SDRAM 17 #define CONFIG_CMD_SH_ZIMAGEBOOT 18 19 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 20 21 #define CONFIG_EXTRA_ENV_SETTINGS \ 22 "bootdevice=0:1\0" \ 23 "usbload=usb reset;usbboot;usb stop;bootm\0" 24 25 #define CONFIG_DISPLAY_BOARDINFO 26 #undef CONFIG_SHOW_BOOT_PROGRESS 27 28 /* MEMORY */ 29 #if defined(CONFIG_SH_32BIT) 30 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 31 /* 0x40000000 - 0x47FFFFFF does not use */ 32 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 33 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 34 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 35 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 36 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 37 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 38 #define SH7785LCR_USB_BASE (0xa6000000) 39 #else 40 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 41 #define SH7785LCR_SDRAM_BASE (0x08000000) 42 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 43 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 44 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 45 #define SH7785LCR_USB_BASE (0xb4000000) 46 #endif 47 48 #define CONFIG_SYS_LONGHELP 49 #define CONFIG_SYS_CBSIZE 256 50 #define CONFIG_SYS_PBSIZE 256 51 #define CONFIG_SYS_MAXARGS 16 52 #define CONFIG_SYS_BARGSIZE 512 53 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 54 55 /* SCIF */ 56 #define CONFIG_CONS_SCIF1 1 57 #define CONFIG_SCIF_EXT_CLOCK 1 58 59 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 60 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 61 (SH7785LCR_SDRAM_SIZE) - \ 62 4 * 1024 * 1024) 63 #undef CONFIG_SYS_ALT_MEMTEST 64 #undef CONFIG_SYS_MEMTEST_SCRATCH 65 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 66 67 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 68 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 69 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 70 71 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 72 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 73 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 74 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 75 76 /* FLASH */ 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #undef CONFIG_SYS_FLASH_QUIET_TEST 80 #define CONFIG_SYS_FLASH_EMPTY_INFO 81 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 82 #define CONFIG_SYS_MAX_FLASH_SECT 512 83 84 #define CONFIG_SYS_MAX_FLASH_BANKS 1 85 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 86 (0 * SH7785LCR_FLASH_BANK_SIZE) } 87 88 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 89 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 90 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 91 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 92 93 #undef CONFIG_SYS_FLASH_PROTECTION 94 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 95 96 /* R8A66597 */ 97 #define CONFIG_USB_R8A66597_HCD 98 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 99 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 100 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 101 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 102 103 /* PCI Controller */ 104 #define CONFIG_SH4_PCI 105 #define CONFIG_SH7780_PCI 106 #if defined(CONFIG_SH_32BIT) 107 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 108 #define CONFIG_SH7780_PCI_LAR 0x5f000000 109 #define CONFIG_SH7780_PCI_BAR 0x5f000000 110 #else 111 #define CONFIG_SH7780_PCI_LSR 0x07f00001 112 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 113 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 114 #endif 115 #define CONFIG_PCI_SCAN_SHOW 1 116 117 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 118 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 119 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 120 121 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 122 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 123 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 124 125 #if defined(CONFIG_SH_32BIT) 126 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 127 #else 128 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 129 #endif 130 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 131 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 132 133 /* ENV setting */ 134 #define CONFIG_ENV_OVERWRITE 1 135 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 136 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 137 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 138 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 139 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 140 141 /* Board Clock */ 142 /* The SCIF used external clock. system clock only used timer. */ 143 #define CONFIG_SYS_CLK_FREQ 50000000 144 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 145 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 146 #define CONFIG_SYS_TMU_CLK_DIV 4 147 148 #endif /* __SH7785LCR_H */ 149