1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #undef DEBUG 13 #define CONFIG_SH 1 14 #define CONFIG_SH4A 1 15 #define CONFIG_CPU_SH7785 1 16 #define CONFIG_SH7785LCR 1 17 18 #define CONFIG_CMD_FLASH 19 #define CONFIG_CMD_MEMORY 20 #define CONFIG_CMD_PCI 21 #define CONFIG_CMD_NET 22 #define CONFIG_CMD_PING 23 #define CONFIG_CMD_NFS 24 #define CONFIG_CMD_SDRAM 25 #define CONFIG_CMD_RUN 26 #define CONFIG_CMD_SAVEENV 27 #define CONFIG_CMD_SH_ZIMAGEBOOT 28 29 #define CONFIG_CMD_USB 30 #define CONFIG_USB_STORAGE 31 #define CONFIG_CMD_EXT2 32 #define CONFIG_CMD_FAT 33 #define CONFIG_DOS_PARTITION 34 #define CONFIG_MAC_PARTITION 35 36 #define CONFIG_BAUDRATE 115200 37 #define CONFIG_BOOTDELAY 3 38 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 39 40 #define CONFIG_EXTRA_ENV_SETTINGS \ 41 "bootdevice=0:1\0" \ 42 "usbload=usb reset;usbboot;usb stop;bootm\0" 43 44 #define CONFIG_VERSION_VARIABLE 45 #undef CONFIG_SHOW_BOOT_PROGRESS 46 47 /* MEMORY */ 48 #if defined(CONFIG_SH_32BIT) 49 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 50 /* 0x40000000 - 0x47FFFFFF does not use */ 51 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 52 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 53 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 54 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 55 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 56 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 57 #define SH7785LCR_USB_BASE (0xa6000000) 58 #else 59 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 60 #define SH7785LCR_SDRAM_BASE (0x08000000) 61 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 62 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 63 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 64 #define SH7785LCR_USB_BASE (0xb4000000) 65 #endif 66 67 #define CONFIG_SYS_LONGHELP 68 #define CONFIG_SYS_PROMPT "=> " 69 #define CONFIG_SYS_CBSIZE 256 70 #define CONFIG_SYS_PBSIZE 256 71 #define CONFIG_SYS_MAXARGS 16 72 #define CONFIG_SYS_BARGSIZE 512 73 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 74 75 /* SCIF */ 76 #define CONFIG_SCIF_CONSOLE 1 77 #define CONFIG_CONS_SCIF1 1 78 #define CONFIG_SCIF_EXT_CLOCK 1 79 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 80 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 81 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 82 83 84 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 85 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 86 (SH7785LCR_SDRAM_SIZE) - \ 87 4 * 1024 * 1024) 88 #undef CONFIG_SYS_ALT_MEMTEST 89 #undef CONFIG_SYS_MEMTEST_SCRATCH 90 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 91 92 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 93 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 94 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 95 96 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 97 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 98 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 99 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 100 101 /* FLASH */ 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #undef CONFIG_SYS_FLASH_QUIET_TEST 105 #define CONFIG_SYS_FLASH_EMPTY_INFO 106 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 107 #define CONFIG_SYS_MAX_FLASH_SECT 512 108 109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 110 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 111 (0 * SH7785LCR_FLASH_BANK_SIZE) } 112 113 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 114 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 115 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 116 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 117 118 #undef CONFIG_SYS_FLASH_PROTECTION 119 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 120 121 /* R8A66597 */ 122 #define CONFIG_USB_R8A66597_HCD 123 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 124 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 125 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 126 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 127 128 /* PCI Controller */ 129 #define CONFIG_PCI 130 #define CONFIG_SH4_PCI 131 #define CONFIG_SH7780_PCI 132 #if defined(CONFIG_SH_32BIT) 133 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 134 #define CONFIG_SH7780_PCI_LAR 0x5f000000 135 #define CONFIG_SH7780_PCI_BAR 0x5f000000 136 #else 137 #define CONFIG_SH7780_PCI_LSR 0x07f00001 138 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 139 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 140 #endif 141 #define CONFIG_PCI_PNP 142 #define CONFIG_PCI_SCAN_SHOW 1 143 144 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 145 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 146 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 147 148 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 149 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 150 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 151 152 #if defined(CONFIG_SH_32BIT) 153 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 154 #else 155 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 156 #endif 157 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 158 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 159 160 /* Network device (RTL8169) support */ 161 #define CONFIG_RTL8169 162 163 /* ENV setting */ 164 #define CONFIG_ENV_IS_IN_FLASH 165 #define CONFIG_ENV_OVERWRITE 1 166 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 167 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 168 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 169 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 170 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 171 172 /* Board Clock */ 173 /* The SCIF used external clock. system clock only used timer. */ 174 #define CONFIG_SYS_CLK_FREQ 50000000 175 #define CONFIG_SYS_TMU_CLK_DIV 4 176 #define CONFIG_SYS_HZ 1000 177 178 #endif /* __SH7785LCR_H */ 179