1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #define CONFIG_CPU_SH7785 1 13 #define CONFIG_SH7785LCR 1 14 15 #define CONFIG_CMD_PCI 16 #define CONFIG_CMD_SDRAM 17 #define CONFIG_CMD_SH_ZIMAGEBOOT 18 19 #define CONFIG_BAUDRATE 115200 20 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 21 22 #define CONFIG_EXTRA_ENV_SETTINGS \ 23 "bootdevice=0:1\0" \ 24 "usbload=usb reset;usbboot;usb stop;bootm\0" 25 26 #define CONFIG_DISPLAY_BOARDINFO 27 #undef CONFIG_SHOW_BOOT_PROGRESS 28 29 /* MEMORY */ 30 #if defined(CONFIG_SH_32BIT) 31 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 32 /* 0x40000000 - 0x47FFFFFF does not use */ 33 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 34 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 35 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 36 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 37 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 38 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 39 #define SH7785LCR_USB_BASE (0xa6000000) 40 #else 41 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 42 #define SH7785LCR_SDRAM_BASE (0x08000000) 43 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 44 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 45 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 46 #define SH7785LCR_USB_BASE (0xb4000000) 47 #endif 48 49 #define CONFIG_SYS_LONGHELP 50 #define CONFIG_SYS_CBSIZE 256 51 #define CONFIG_SYS_PBSIZE 256 52 #define CONFIG_SYS_MAXARGS 16 53 #define CONFIG_SYS_BARGSIZE 512 54 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 55 56 /* SCIF */ 57 #define CONFIG_SCIF_CONSOLE 1 58 #define CONFIG_CONS_SCIF1 1 59 #define CONFIG_SCIF_EXT_CLOCK 1 60 61 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 62 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 63 (SH7785LCR_SDRAM_SIZE) - \ 64 4 * 1024 * 1024) 65 #undef CONFIG_SYS_ALT_MEMTEST 66 #undef CONFIG_SYS_MEMTEST_SCRATCH 67 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 68 69 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 70 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 71 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 72 73 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 74 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 75 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 76 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 77 78 /* FLASH */ 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #undef CONFIG_SYS_FLASH_QUIET_TEST 82 #define CONFIG_SYS_FLASH_EMPTY_INFO 83 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 84 #define CONFIG_SYS_MAX_FLASH_SECT 512 85 86 #define CONFIG_SYS_MAX_FLASH_BANKS 1 87 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 88 (0 * SH7785LCR_FLASH_BANK_SIZE) } 89 90 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 91 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 92 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 93 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 94 95 #undef CONFIG_SYS_FLASH_PROTECTION 96 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 97 98 /* R8A66597 */ 99 #define CONFIG_USB_R8A66597_HCD 100 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 101 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 102 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 103 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 104 105 /* PCI Controller */ 106 #define CONFIG_SH4_PCI 107 #define CONFIG_SH7780_PCI 108 #if defined(CONFIG_SH_32BIT) 109 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 110 #define CONFIG_SH7780_PCI_LAR 0x5f000000 111 #define CONFIG_SH7780_PCI_BAR 0x5f000000 112 #else 113 #define CONFIG_SH7780_PCI_LSR 0x07f00001 114 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 115 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 116 #endif 117 #define CONFIG_PCI_SCAN_SHOW 1 118 119 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 120 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 121 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 122 123 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 124 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 125 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 126 127 #if defined(CONFIG_SH_32BIT) 128 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 129 #else 130 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 131 #endif 132 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 133 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 134 135 /* ENV setting */ 136 #define CONFIG_ENV_IS_IN_FLASH 137 #define CONFIG_ENV_OVERWRITE 1 138 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 139 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 140 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 141 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 142 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 143 144 /* Board Clock */ 145 /* The SCIF used external clock. system clock only used timer. */ 146 #define CONFIG_SYS_CLK_FREQ 50000000 147 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 148 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 149 #define CONFIG_SYS_TMU_CLK_DIV 4 150 151 #endif /* __SH7785LCR_H */ 152