1 /* 2 * Configuation settings for the Renesas SH7763RDP board 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __SH7763RDP_H 11 #define __SH7763RDP_H 12 13 #define CONFIG_CPU_SH7763 1 14 #define CONFIG_SH7763RDP 1 15 #define __LITTLE_ENDIAN 1 16 17 /* 18 * Command line configuration. 19 */ 20 #define CONFIG_CMD_SDRAM 21 #define CONFIG_CMD_FLASH 22 #define CONFIG_CMD_MEMORY 23 #define CONFIG_CMD_NET 24 #define CONFIG_CMD_MII 25 #define CONFIG_CMD_PING 26 #define CONFIG_CMD_SAVEENV 27 #define CONFIG_CMD_NFS 28 #define CONFIG_CMD_JFFS2 29 30 #define CONFIG_BOOTDELAY -1 31 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" 32 #define CONFIG_ENV_OVERWRITE 1 33 34 #define CONFIG_VERSION_VARIABLE 35 #undef CONFIG_SHOW_BOOT_PROGRESS 36 37 /* SCIF */ 38 #define CONFIG_SCIF_CONSOLE 1 39 #define CONFIG_BAUDRATE 115200 40 #define CONFIG_CONS_SCIF2 1 41 42 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 43 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 44 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 45 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 46 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 47 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments 48 passed to kernel */ 49 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 50 settings for this board */ 51 52 /* SDRAM */ 53 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 54 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 55 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 56 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 57 58 /* Flash(NOR) */ 59 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 60 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 61 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 62 #define CONFIG_SYS_MAX_FLASH_SECT (520) 63 64 /* U-boot setting */ 65 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 66 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 67 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 68 /* Size of DRAM reserved for malloc() use */ 69 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 70 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 71 72 #define CONFIG_SYS_FLASH_CFI 73 #define CONFIG_FLASH_CFI_DRIVER 74 #undef CONFIG_SYS_FLASH_QUIET_TEST 75 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 76 /* Timeout for Flash erase operations (in ms) */ 77 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 78 /* Timeout for Flash write operations (in ms) */ 79 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 80 /* Timeout for Flash set sector lock bit operations (in ms) */ 81 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 82 /* Timeout for Flash clear lock bit operations (in ms) */ 83 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 84 /* Use hardware flash sectors protection instead of U-Boot software protection */ 85 #undef CONFIG_SYS_FLASH_PROTECTION 86 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 87 #define CONFIG_ENV_IS_IN_FLASH 88 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 89 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 90 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 91 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 92 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 93 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 94 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 95 96 /* Clock */ 97 #define CONFIG_SYS_CLK_FREQ 66666666 98 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 99 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 100 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 101 102 /* Ether */ 103 #define CONFIG_SH_ETHER 1 104 #define CONFIG_SH_ETHER_USE_PORT (1) 105 #define CONFIG_SH_ETHER_PHY_ADDR (0x01) 106 #define CONFIG_PHYLIB 107 #define CONFIG_BITBANGMII 108 #define CONFIG_BITBANGMII_MULTI 109 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 110 111 #endif /* __SH7763RDP_H */ 112