1 /* 2 * Configuation settings for the Renesas SH7763RDP board 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __SH7763RDP_H 11 #define __SH7763RDP_H 12 13 #define CONFIG_CPU_SH7763 1 14 #define CONFIG_SH7763RDP 1 15 #define __LITTLE_ENDIAN 1 16 17 /* 18 * Command line configuration. 19 */ 20 #define CONFIG_CMD_SDRAM 21 22 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" 23 #define CONFIG_ENV_OVERWRITE 1 24 25 #define CONFIG_DISPLAY_BOARDINFO 26 #undef CONFIG_SHOW_BOOT_PROGRESS 27 28 /* SCIF */ 29 #define CONFIG_CONS_SCIF2 1 30 31 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 32 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 33 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 34 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 35 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 36 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments 37 passed to kernel */ 38 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 39 settings for this board */ 40 41 /* SDRAM */ 42 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 43 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 44 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 46 47 /* Flash(NOR) */ 48 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 49 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 50 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 51 #define CONFIG_SYS_MAX_FLASH_SECT (520) 52 53 /* U-Boot setting */ 54 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 55 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 56 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 57 /* Size of DRAM reserved for malloc() use */ 58 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 59 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 60 61 #define CONFIG_SYS_FLASH_CFI 62 #define CONFIG_FLASH_CFI_DRIVER 63 #undef CONFIG_SYS_FLASH_QUIET_TEST 64 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 65 /* Timeout for Flash erase operations (in ms) */ 66 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 67 /* Timeout for Flash write operations (in ms) */ 68 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 69 /* Timeout for Flash set sector lock bit operations (in ms) */ 70 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 71 /* Timeout for Flash clear lock bit operations (in ms) */ 72 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 73 /* Use hardware flash sectors protection instead of U-Boot software protection */ 74 #undef CONFIG_SYS_FLASH_PROTECTION 75 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 76 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 77 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 78 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 79 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 80 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 81 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 82 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 83 84 /* Clock */ 85 #define CONFIG_SYS_CLK_FREQ 66666666 86 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 87 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 88 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 89 90 /* Ether */ 91 #define CONFIG_SH_ETHER 1 92 #define CONFIG_SH_ETHER_USE_PORT (1) 93 #define CONFIG_SH_ETHER_PHY_ADDR (0x01) 94 #define CONFIG_PHYLIB 95 #define CONFIG_BITBANGMII 96 #define CONFIG_BITBANGMII_MULTI 97 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 98 99 #endif /* __SH7763RDP_H */ 100