1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR 1 14 #define CONFIG_SH7757LCR_DDR_ECC 1 15 16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 #undef CONFIG_SHOW_BOOT_PROGRESS 20 21 /* MEMORY */ 22 #define SH7757LCR_SDRAM_BASE (0x80000000) 23 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 24 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 25 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 26 27 #define CONFIG_SYS_LONGHELP 28 #define CONFIG_SYS_CBSIZE 256 29 #define CONFIG_SYS_PBSIZE 256 30 #define CONFIG_SYS_MAXARGS 16 31 #define CONFIG_SYS_BARGSIZE 512 32 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 33 34 /* SCIF */ 35 #define CONFIG_CONS_SCIF2 1 36 37 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 38 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 39 224 * 1024 * 1024) 40 #undef CONFIG_SYS_ALT_MEMTEST 41 #undef CONFIG_SYS_MEMTEST_SCRATCH 42 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 43 44 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 45 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 46 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 47 (128 + 16) * 1024 * 1024) 48 49 #define CONFIG_SYS_MONITOR_BASE 0x00000000 50 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 51 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 52 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 53 54 /* Ether */ 55 #define CONFIG_SH_ETHER 1 56 #define CONFIG_SH_ETHER_USE_PORT 0 57 #define CONFIG_SH_ETHER_PHY_ADDR 1 58 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 59 #define CONFIG_BITBANGMII 60 #define CONFIG_BITBANGMII_MULTI 61 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 62 63 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 64 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 65 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 66 #define SH7757LCR_ETHERNET_MAC_SIZE 17 67 #define SH7757LCR_ETHERNET_NUM_CH 2 68 69 /* Gigabit Ether */ 70 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 71 72 /* SPI */ 73 #define CONFIG_SH_SPI 1 74 #define CONFIG_SH_SPI_BASE 0xfe002000 75 76 /* MMCIF */ 77 #define CONFIG_SH_MMCIF 1 78 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 79 #define CONFIG_SH_MMCIF_CLK 48000000 80 81 /* SH7757 board */ 82 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 83 #define SH7757LCR_GRA_OFFSET 0x1f000000 84 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 85 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 86 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 87 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 88 89 /* ENV setting */ 90 #define CONFIG_ENV_IS_EMBEDDED 91 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 92 #define CONFIG_ENV_ADDR (0x00080000) 93 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 94 #define CONFIG_ENV_OVERWRITE 1 95 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 96 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 97 #define CONFIG_EXTRA_ENV_SETTINGS \ 98 "netboot=bootp; bootm\0" 99 100 /* Board Clock */ 101 #define CONFIG_SYS_CLK_FREQ 48000000 102 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 103 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 104 #define CONFIG_SYS_TMU_CLK_DIV 4 105 #endif /* __SH7757LCR_H */ 106