1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7757 1 14 #define CONFIG_SH7757LCR 1 15 #define CONFIG_SH7757LCR_DDR_ECC 1 16 17 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 18 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" 19 20 #define CONFIG_CMD_SDRAM 21 #define CONFIG_CMD_MD5SUM 22 #define CONFIG_MD5 23 #define CONFIG_DOS_PARTITION 24 #define CONFIG_MAC_PARTITION 25 26 #define CONFIG_BAUDRATE 115200 27 #define CONFIG_BOOTDELAY 3 28 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 29 30 #define CONFIG_VERSION_VARIABLE 31 #undef CONFIG_SHOW_BOOT_PROGRESS 32 33 /* MEMORY */ 34 #define SH7757LCR_SDRAM_BASE (0x80000000) 35 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 36 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 37 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 38 39 #define CONFIG_SYS_LONGHELP 40 #define CONFIG_SYS_CBSIZE 256 41 #define CONFIG_SYS_PBSIZE 256 42 #define CONFIG_SYS_MAXARGS 16 43 #define CONFIG_SYS_BARGSIZE 512 44 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 45 46 /* SCIF */ 47 #define CONFIG_SCIF_CONSOLE 1 48 #define CONFIG_CONS_SCIF2 1 49 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 50 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 51 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 52 53 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 54 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 55 224 * 1024 * 1024) 56 #undef CONFIG_SYS_ALT_MEMTEST 57 #undef CONFIG_SYS_MEMTEST_SCRATCH 58 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 59 60 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 61 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 62 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 63 (128 + 16) * 1024 * 1024) 64 65 #define CONFIG_SYS_MONITOR_BASE 0x00000000 66 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 67 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 68 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 69 70 /* FLASH */ 71 #define CONFIG_SYS_NO_FLASH 72 73 /* Ether */ 74 #define CONFIG_SH_ETHER 1 75 #define CONFIG_SH_ETHER_USE_PORT 0 76 #define CONFIG_SH_ETHER_PHY_ADDR 1 77 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 78 #define CONFIG_PHYLIB 79 #define CONFIG_BITBANGMII 80 #define CONFIG_BITBANGMII_MULTI 81 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 82 83 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 84 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 85 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 86 #define SH7757LCR_ETHERNET_MAC_SIZE 17 87 #define SH7757LCR_ETHERNET_NUM_CH 2 88 #define CONFIG_BOARD_LATE_INIT 89 90 /* Gigabit Ether */ 91 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 92 93 /* SPI */ 94 #define CONFIG_SH_SPI 1 95 #define CONFIG_SH_SPI_BASE 0xfe002000 96 97 /* MMCIF */ 98 #define CONFIG_MMC 1 99 #define CONFIG_GENERIC_MMC 1 100 #define CONFIG_SH_MMCIF 1 101 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 102 #define CONFIG_SH_MMCIF_CLK 48000000 103 104 /* SH7757 board */ 105 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 106 #define SH7757LCR_GRA_OFFSET 0x1f000000 107 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 108 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 109 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 110 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 111 112 /* ENV setting */ 113 #define CONFIG_ENV_IS_EMBEDDED 114 #define CONFIG_ENV_IS_IN_SPI_FLASH 115 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 116 #define CONFIG_ENV_ADDR (0x00080000) 117 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 118 #define CONFIG_ENV_OVERWRITE 1 119 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 120 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "netboot=bootp; bootm\0" 123 124 /* Board Clock */ 125 #define CONFIG_SYS_CLK_FREQ 48000000 126 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 127 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 128 #define CONFIG_SYS_TMU_CLK_DIV 4 129 #endif /* __SH7757LCR_H */ 130