1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7757 1 14 #define CONFIG_SH7757LCR 1 15 #define CONFIG_SH7757LCR_DDR_ECC 1 16 17 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 18 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" 19 20 #define CONFIG_CMD_MEMORY 21 #define CONFIG_CMD_NET 22 #define CONFIG_CMD_MII 23 #define CONFIG_CMD_PING 24 #define CONFIG_CMD_NFS 25 #define CONFIG_CMD_SDRAM 26 #define CONFIG_CMD_SF 27 #define CONFIG_CMD_RUN 28 #define CONFIG_CMD_SAVEENV 29 #define CONFIG_CMD_MD5SUM 30 #define CONFIG_MD5 31 #define CONFIG_CMD_LOADS 32 #define CONFIG_CMD_MMC 33 #define CONFIG_CMD_EXT2 34 #define CONFIG_DOS_PARTITION 35 #define CONFIG_MAC_PARTITION 36 37 #define CONFIG_BAUDRATE 115200 38 #define CONFIG_BOOTDELAY 3 39 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 40 41 #define CONFIG_VERSION_VARIABLE 42 #undef CONFIG_SHOW_BOOT_PROGRESS 43 44 /* MEMORY */ 45 #define SH7757LCR_SDRAM_BASE (0x80000000) 46 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 47 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 48 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 49 50 #define CONFIG_SYS_LONGHELP 51 #define CONFIG_SYS_CBSIZE 256 52 #define CONFIG_SYS_PBSIZE 256 53 #define CONFIG_SYS_MAXARGS 16 54 #define CONFIG_SYS_BARGSIZE 512 55 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 56 57 /* SCIF */ 58 #define CONFIG_SCIF_CONSOLE 1 59 #define CONFIG_CONS_SCIF2 1 60 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 61 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 62 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 63 64 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 66 224 * 1024 * 1024) 67 #undef CONFIG_SYS_ALT_MEMTEST 68 #undef CONFIG_SYS_MEMTEST_SCRATCH 69 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 70 71 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 72 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 73 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 74 (128 + 16) * 1024 * 1024) 75 76 #define CONFIG_SYS_MONITOR_BASE 0x00000000 77 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 78 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 79 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 80 81 /* FLASH */ 82 #define CONFIG_SYS_NO_FLASH 83 84 /* Ether */ 85 #define CONFIG_SH_ETHER 1 86 #define CONFIG_SH_ETHER_USE_PORT 0 87 #define CONFIG_SH_ETHER_PHY_ADDR 1 88 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 89 #define CONFIG_PHYLIB 90 #define CONFIG_BITBANGMII 91 #define CONFIG_BITBANGMII_MULTI 92 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 93 94 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 95 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 96 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 97 #define SH7757LCR_ETHERNET_MAC_SIZE 17 98 #define SH7757LCR_ETHERNET_NUM_CH 2 99 #define CONFIG_BOARD_LATE_INIT 100 101 /* Gigabit Ether */ 102 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 103 104 /* SPI */ 105 #define CONFIG_SH_SPI 1 106 #define CONFIG_SH_SPI_BASE 0xfe002000 107 #define CONFIG_SPI_FLASH 108 #define CONFIG_SPI_FLASH_STMICRO 1 109 110 /* MMCIF */ 111 #define CONFIG_MMC 1 112 #define CONFIG_GENERIC_MMC 1 113 #define CONFIG_SH_MMCIF 1 114 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 115 #define CONFIG_SH_MMCIF_CLK 48000000 116 117 /* SH7757 board */ 118 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 119 #define SH7757LCR_GRA_OFFSET 0x1f000000 120 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 121 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 122 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 123 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 124 125 /* ENV setting */ 126 #define CONFIG_ENV_IS_EMBEDDED 127 #define CONFIG_ENV_IS_IN_SPI_FLASH 128 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 129 #define CONFIG_ENV_ADDR (0x00080000) 130 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 131 #define CONFIG_ENV_OVERWRITE 1 132 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 133 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 134 #define CONFIG_EXTRA_ENV_SETTINGS \ 135 "netboot=bootp; bootm\0" 136 137 /* Board Clock */ 138 #define CONFIG_SYS_CLK_FREQ 48000000 139 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 140 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 141 #define CONFIG_SYS_TMU_CLK_DIV 4 142 #endif /* __SH7757LCR_H */ 143