1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR_DDR_ECC 1 14 15 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 16 17 #define CONFIG_DISPLAY_BOARDINFO 18 #undef CONFIG_SHOW_BOOT_PROGRESS 19 20 /* MEMORY */ 21 #define SH7757LCR_SDRAM_BASE (0x80000000) 22 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 23 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 24 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 25 26 #define CONFIG_SYS_LONGHELP 27 #define CONFIG_SYS_PBSIZE 256 28 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 29 30 /* SCIF */ 31 #define CONFIG_CONS_SCIF2 1 32 33 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 34 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 35 224 * 1024 * 1024) 36 #undef CONFIG_SYS_ALT_MEMTEST 37 #undef CONFIG_SYS_MEMTEST_SCRATCH 38 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 39 40 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 41 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 42 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 43 (128 + 16) * 1024 * 1024) 44 45 #define CONFIG_SYS_MONITOR_BASE 0x00000000 46 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 47 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 48 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 49 50 /* Ether */ 51 #define CONFIG_SH_ETHER_USE_PORT 0 52 #define CONFIG_SH_ETHER_PHY_ADDR 1 53 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 54 #define CONFIG_BITBANGMII 55 #define CONFIG_BITBANGMII_MULTI 56 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 57 58 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 59 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 60 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 61 #define SH7757LCR_ETHERNET_MAC_SIZE 17 62 #define SH7757LCR_ETHERNET_NUM_CH 2 63 64 /* Gigabit Ether */ 65 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 66 67 /* SPI */ 68 #define CONFIG_SH_SPI 1 69 #define CONFIG_SH_SPI_BASE 0xfe002000 70 71 /* MMCIF */ 72 #define CONFIG_SH_MMCIF 1 73 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 74 #define CONFIG_SH_MMCIF_CLK 48000000 75 76 /* SH7757 board */ 77 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 78 #define SH7757LCR_GRA_OFFSET 0x1f000000 79 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 80 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 81 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 82 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 83 84 /* ENV setting */ 85 #define CONFIG_ENV_IS_EMBEDDED 86 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 87 #define CONFIG_ENV_ADDR (0x00080000) 88 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 89 #define CONFIG_ENV_OVERWRITE 1 90 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 91 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "netboot=bootp; bootm\0" 94 95 /* Board Clock */ 96 #define CONFIG_SYS_CLK_FREQ 48000000 97 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 98 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 99 #define CONFIG_SYS_TMU_CLK_DIV 4 100 #endif /* __SH7757LCR_H */ 101