1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __SH7757LCR_H 26 #define __SH7757LCR_H 27 28 #undef DEBUG 29 #define CONFIG_SH 1 30 #define CONFIG_SH4A 1 31 #define CONFIG_SH_32BIT 1 32 #define CONFIG_CPU_SH7757 1 33 #define CONFIG_SH7757LCR 1 34 35 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 36 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" 37 38 #define CONFIG_CMD_MEMORY 39 #define CONFIG_CMD_NET 40 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_NFS 42 #define CONFIG_CMD_DFL 43 #define CONFIG_CMD_SDRAM 44 #define CONFIG_CMD_SF 45 #define CONFIG_CMD_RUN 46 #define CONFIG_CMD_SAVEENV 47 #define CONFIG_CMD_MD5SUM 48 #define CONFIG_MD5 49 #define CONFIG_CMD_LOADS 50 51 #define CONFIG_BAUDRATE 115200 52 #define CONFIG_BOOTDELAY 3 53 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 54 55 #define CONFIG_VERSION_VARIABLE 56 #undef CONFIG_SHOW_BOOT_PROGRESS 57 58 /* MEMORY */ 59 #define SH7757LCR_SDRAM_BASE (0x80000000) 60 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 61 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 62 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 63 64 #define CONFIG_SYS_LONGHELP 65 #define CONFIG_SYS_PROMPT "=> " 66 #define CONFIG_SYS_CBSIZE 256 67 #define CONFIG_SYS_PBSIZE 256 68 #define CONFIG_SYS_MAXARGS 16 69 #define CONFIG_SYS_BARGSIZE 512 70 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 71 72 /* SCIF */ 73 #define CONFIG_SCIF_CONSOLE 1 74 #define CONFIG_CONS_SCIF2 1 75 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 76 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 77 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 78 79 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 80 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 81 224 * 1024 * 1024) 82 #undef CONFIG_SYS_ALT_MEMTEST 83 #undef CONFIG_SYS_MEMTEST_SCRATCH 84 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 85 86 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 87 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 88 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 89 (128 + 16) * 1024 * 1024) 90 91 #define CONFIG_SYS_MONITOR_BASE 0x00000000 92 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 93 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 94 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 95 96 /* FLASH */ 97 #define CONFIG_SYS_NO_FLASH 98 99 /* Ether */ 100 #define CONFIG_SH_ETHER 1 101 #define CONFIG_SH_ETHER_USE_PORT 0 102 #define CONFIG_SH_ETHER_PHY_ADDR 1 103 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 104 105 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 106 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 107 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 108 #define SH7757LCR_ETHERNET_MAC_SIZE 17 109 #define SH7757LCR_ETHERNET_NUM_CH 2 110 #define CONFIG_BOARD_LATE_INIT 111 112 /* Gigabit Ether */ 113 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 114 115 /* SPI */ 116 #define CONFIG_SH_SPI 1 117 #define CONFIG_SH_SPI_BASE 0xfe002000 118 #define CONFIG_SPI_FLASH 119 #define CONFIG_SPI_FLASH_STMICRO 1 120 121 /* SH7757 board */ 122 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 123 #define SH7757LCR_GRA_OFFSET 0x1f000000 124 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 125 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 126 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 127 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 128 129 /* ENV setting */ 130 #define CONFIG_ENV_IS_EMBEDDED 131 #define CONFIG_ENV_IS_IN_SPI_FLASH 132 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 133 #define CONFIG_ENV_ADDR (0x00080000) 134 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 135 #define CONFIG_ENV_OVERWRITE 1 136 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 137 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "netboot=bootp; bootm\0" 140 141 /* Board Clock */ 142 #define CONFIG_SYS_CLK_FREQ 48000000 143 #define CONFIG_SYS_TMU_CLK_DIV 4 144 #define CONFIG_SYS_HZ 1000 145 #endif /* __SH7757LCR_H */ 146