1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR 1 14 #define CONFIG_SH7757LCR_DDR_ECC 1 15 16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17 18 #define CONFIG_CMD_SDRAM 19 #define CONFIG_CMD_MD5SUM 20 #define CONFIG_MD5 21 #define CONFIG_DOS_PARTITION 22 #define CONFIG_MAC_PARTITION 23 24 #define CONFIG_BAUDRATE 115200 25 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 26 27 #define CONFIG_DISPLAY_BOARDINFO 28 #undef CONFIG_SHOW_BOOT_PROGRESS 29 30 /* MEMORY */ 31 #define SH7757LCR_SDRAM_BASE (0x80000000) 32 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 33 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 34 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 35 36 #define CONFIG_SYS_LONGHELP 37 #define CONFIG_SYS_CBSIZE 256 38 #define CONFIG_SYS_PBSIZE 256 39 #define CONFIG_SYS_MAXARGS 16 40 #define CONFIG_SYS_BARGSIZE 512 41 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 42 43 /* SCIF */ 44 #define CONFIG_SCIF_CONSOLE 1 45 #define CONFIG_CONS_SCIF2 1 46 47 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 48 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 49 224 * 1024 * 1024) 50 #undef CONFIG_SYS_ALT_MEMTEST 51 #undef CONFIG_SYS_MEMTEST_SCRATCH 52 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 53 54 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 55 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 56 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 57 (128 + 16) * 1024 * 1024) 58 59 #define CONFIG_SYS_MONITOR_BASE 0x00000000 60 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 61 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 62 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 63 64 /* FLASH */ 65 #define CONFIG_SYS_NO_FLASH 66 67 /* Ether */ 68 #define CONFIG_SH_ETHER 1 69 #define CONFIG_SH_ETHER_USE_PORT 0 70 #define CONFIG_SH_ETHER_PHY_ADDR 1 71 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 72 #define CONFIG_PHYLIB 73 #define CONFIG_BITBANGMII 74 #define CONFIG_BITBANGMII_MULTI 75 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 76 77 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 78 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 79 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 80 #define SH7757LCR_ETHERNET_MAC_SIZE 17 81 #define SH7757LCR_ETHERNET_NUM_CH 2 82 #define CONFIG_BOARD_LATE_INIT 83 84 /* Gigabit Ether */ 85 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 86 87 /* SPI */ 88 #define CONFIG_SH_SPI 1 89 #define CONFIG_SH_SPI_BASE 0xfe002000 90 91 /* MMCIF */ 92 #define CONFIG_MMC 1 93 #define CONFIG_GENERIC_MMC 1 94 #define CONFIG_SH_MMCIF 1 95 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 96 #define CONFIG_SH_MMCIF_CLK 48000000 97 98 /* SH7757 board */ 99 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 100 #define SH7757LCR_GRA_OFFSET 0x1f000000 101 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 102 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 103 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 104 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 105 106 /* ENV setting */ 107 #define CONFIG_ENV_IS_EMBEDDED 108 #define CONFIG_ENV_IS_IN_SPI_FLASH 109 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 110 #define CONFIG_ENV_ADDR (0x00080000) 111 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 112 #define CONFIG_ENV_OVERWRITE 1 113 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 114 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 115 #define CONFIG_EXTRA_ENV_SETTINGS \ 116 "netboot=bootp; bootm\0" 117 118 /* Board Clock */ 119 #define CONFIG_SYS_CLK_FREQ 48000000 120 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 121 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 122 #define CONFIG_SYS_TMU_CLK_DIV 4 123 #endif /* __SH7757LCR_H */ 124