1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __SH7757LCR_H 26 #define __SH7757LCR_H 27 28 #undef DEBUG 29 #define CONFIG_SH 1 30 #define CONFIG_SH4A 1 31 #define CONFIG_SH_32BIT 1 32 #define CONFIG_CPU_SH7757 1 33 #define CONFIG_SH7757LCR 1 34 #define CONFIG_SH7757LCR_DDR_ECC 1 35 36 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 37 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" 38 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_NET 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_PING 43 #define CONFIG_CMD_NFS 44 #define CONFIG_CMD_DFL 45 #define CONFIG_CMD_SDRAM 46 #define CONFIG_CMD_SF 47 #define CONFIG_CMD_RUN 48 #define CONFIG_CMD_SAVEENV 49 #define CONFIG_CMD_MD5SUM 50 #define CONFIG_MD5 51 #define CONFIG_CMD_LOADS 52 #define CONFIG_CMD_MMC 53 #define CONFIG_CMD_EXT2 54 #define CONFIG_DOS_PARTITION 55 #define CONFIG_MAC_PARTITION 56 57 #define CONFIG_BAUDRATE 115200 58 #define CONFIG_BOOTDELAY 3 59 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 60 61 #define CONFIG_VERSION_VARIABLE 62 #undef CONFIG_SHOW_BOOT_PROGRESS 63 64 /* MEMORY */ 65 #define SH7757LCR_SDRAM_BASE (0x80000000) 66 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 67 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 68 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 69 70 #define CONFIG_SYS_LONGHELP 71 #define CONFIG_SYS_PROMPT "=> " 72 #define CONFIG_SYS_CBSIZE 256 73 #define CONFIG_SYS_PBSIZE 256 74 #define CONFIG_SYS_MAXARGS 16 75 #define CONFIG_SYS_BARGSIZE 512 76 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 77 78 /* SCIF */ 79 #define CONFIG_SCIF_CONSOLE 1 80 #define CONFIG_CONS_SCIF2 1 81 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 82 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 83 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 84 85 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 87 224 * 1024 * 1024) 88 #undef CONFIG_SYS_ALT_MEMTEST 89 #undef CONFIG_SYS_MEMTEST_SCRATCH 90 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 91 92 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 93 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 94 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 95 (128 + 16) * 1024 * 1024) 96 97 #define CONFIG_SYS_MONITOR_BASE 0x00000000 98 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 99 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 100 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 101 102 /* FLASH */ 103 #define CONFIG_SYS_NO_FLASH 104 105 /* Ether */ 106 #define CONFIG_SH_ETHER 1 107 #define CONFIG_SH_ETHER_USE_PORT 0 108 #define CONFIG_SH_ETHER_PHY_ADDR 1 109 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 110 #define CONFIG_PHYLIB 111 #define CONFIG_BITBANGMII 112 #define CONFIG_BITBANGMII_MULTI 113 114 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 115 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 116 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 117 #define SH7757LCR_ETHERNET_MAC_SIZE 17 118 #define SH7757LCR_ETHERNET_NUM_CH 2 119 #define CONFIG_BOARD_LATE_INIT 120 121 /* Gigabit Ether */ 122 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 123 124 /* SPI */ 125 #define CONFIG_SH_SPI 1 126 #define CONFIG_SH_SPI_BASE 0xfe002000 127 #define CONFIG_SPI_FLASH 128 #define CONFIG_SPI_FLASH_STMICRO 1 129 130 /* MMCIF */ 131 #define CONFIG_MMC 1 132 #define CONFIG_GENERIC_MMC 1 133 #define CONFIG_SH_MMCIF 1 134 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 135 #define CONFIG_SH_MMCIF_CLK 48000000 136 137 /* SH7757 board */ 138 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 139 #define SH7757LCR_GRA_OFFSET 0x1f000000 140 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 141 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 142 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 143 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 144 145 /* ENV setting */ 146 #define CONFIG_ENV_IS_EMBEDDED 147 #define CONFIG_ENV_IS_IN_SPI_FLASH 148 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 149 #define CONFIG_ENV_ADDR (0x00080000) 150 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 151 #define CONFIG_ENV_OVERWRITE 1 152 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 153 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 154 #define CONFIG_EXTRA_ENV_SETTINGS \ 155 "netboot=bootp; bootm\0" 156 157 /* Board Clock */ 158 #define CONFIG_SYS_CLK_FREQ 48000000 159 #define CONFIG_SYS_TMU_CLK_DIV 4 160 #define CONFIG_SYS_HZ 1000 161 #endif /* __SH7757LCR_H */ 162