xref: /openbmc/u-boot/include/configs/sh7757lcr.h (revision 0f44d33536a50ef65259c322fa2d4a058585caf9)
1 /*
2  * Configuation settings for the sh7757lcr board
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __SH7757LCR_H
10 #define __SH7757LCR_H
11 
12 #define CONFIG_CPU_SH7757	1
13 #define CONFIG_SH7757LCR_DDR_ECC	1
14 
15 #define CONFIG_DISPLAY_BOARDINFO
16 #undef	CONFIG_SHOW_BOOT_PROGRESS
17 
18 /* MEMORY */
19 #define SH7757LCR_SDRAM_BASE		(0x80000000)
20 #define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
21 #define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
22 #define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
23 
24 #define CONFIG_SYS_LONGHELP
25 #define CONFIG_SYS_PBSIZE		256
26 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
27 
28 /* SCIF */
29 #define CONFIG_CONS_SCIF2	1
30 
31 #define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
32 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
33 					 224 * 1024 * 1024)
34 #undef	CONFIG_SYS_ALT_MEMTEST
35 #undef	CONFIG_SYS_MEMTEST_SCRATCH
36 #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
37 
38 #define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
39 #define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
40 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
41 					 (128 + 16) * 1024 * 1024)
42 
43 #define CONFIG_SYS_MONITOR_BASE		0x00000000
44 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
45 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
46 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
47 
48 /* Ether */
49 #define CONFIG_SH_ETHER_USE_PORT	0
50 #define CONFIG_SH_ETHER_PHY_ADDR	1
51 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
52 #define CONFIG_BITBANGMII
53 #define CONFIG_BITBANGMII_MULTI
54 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
55 
56 #define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
57 #define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
58 #define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
59 #define SH7757LCR_ETHERNET_MAC_SIZE	17
60 #define SH7757LCR_ETHERNET_NUM_CH	2
61 
62 /* Gigabit Ether */
63 #define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
64 
65 /* SPI */
66 #define CONFIG_SH_SPI_BASE		0xfe002000
67 
68 /* MMCIF */
69 #define CONFIG_SH_MMCIF			1
70 #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
71 #define CONFIG_SH_MMCIF_CLK		48000000
72 
73 /* SH7757 board */
74 #define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
75 #define SH7757LCR_GRA_OFFSET		0x1f000000
76 #define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
77 #define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
78 #define SH7757LCR_PCIEBRG_ADDR		0x00090000
79 #define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
80 
81 /* ENV setting */
82 #define CONFIG_ENV_IS_EMBEDDED
83 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
84 #define CONFIG_ENV_ADDR		(0x00080000)
85 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
86 #define CONFIG_ENV_OVERWRITE	1
87 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
88 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
89 #define CONFIG_EXTRA_ENV_SETTINGS				\
90 		"netboot=bootp; bootm\0"
91 
92 /* Board Clock */
93 #define CONFIG_SYS_CLK_FREQ	48000000
94 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
95 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
96 #define CONFIG_SYS_TMU_CLK_DIV	4
97 #endif	/* __SH7757LCR_H */
98