1*320cf350SYoshihiro Shimoda /* 2*320cf350SYoshihiro Shimoda * Configuation settings for the sh7753evb board 3*320cf350SYoshihiro Shimoda * 4*320cf350SYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 5*320cf350SYoshihiro Shimoda * 6*320cf350SYoshihiro Shimoda * SPDX-License-Identifier: GPL-2.0+ 7*320cf350SYoshihiro Shimoda */ 8*320cf350SYoshihiro Shimoda 9*320cf350SYoshihiro Shimoda #ifndef __SH7753EVB_H 10*320cf350SYoshihiro Shimoda #define __SH7753EVB_H 11*320cf350SYoshihiro Shimoda 12*320cf350SYoshihiro Shimoda #undef DEBUG 13*320cf350SYoshihiro Shimoda #define CONFIG_SH 1 14*320cf350SYoshihiro Shimoda #define CONFIG_SH4A 1 15*320cf350SYoshihiro Shimoda #define CONFIG_SH_32BIT 1 16*320cf350SYoshihiro Shimoda #define CONFIG_CPU_SH7753 1 17*320cf350SYoshihiro Shimoda #define CONFIG_SH7753EVB 1 18*320cf350SYoshihiro Shimoda 19*320cf350SYoshihiro Shimoda #define CONFIG_SYS_TEXT_BASE 0x5ff80000 20*320cf350SYoshihiro Shimoda #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds" 21*320cf350SYoshihiro Shimoda 22*320cf350SYoshihiro Shimoda #define CONFIG_CMD_MEMORY 23*320cf350SYoshihiro Shimoda #define CONFIG_CMD_NET 24*320cf350SYoshihiro Shimoda #define CONFIG_CMD_MII 25*320cf350SYoshihiro Shimoda #define CONFIG_CMD_PING 26*320cf350SYoshihiro Shimoda #define CONFIG_CMD_NFS 27*320cf350SYoshihiro Shimoda #define CONFIG_CMD_DFL 28*320cf350SYoshihiro Shimoda #define CONFIG_CMD_SDRAM 29*320cf350SYoshihiro Shimoda #define CONFIG_CMD_SF 30*320cf350SYoshihiro Shimoda #define CONFIG_CMD_RUN 31*320cf350SYoshihiro Shimoda #define CONFIG_CMD_SAVEENV 32*320cf350SYoshihiro Shimoda #define CONFIG_CMD_MD5SUM 33*320cf350SYoshihiro Shimoda #define CONFIG_MD5 34*320cf350SYoshihiro Shimoda #define CONFIG_CMD_LOADS 35*320cf350SYoshihiro Shimoda #define CONFIG_CMD_MMC 36*320cf350SYoshihiro Shimoda #define CONFIG_CMD_EXT2 37*320cf350SYoshihiro Shimoda #define CONFIG_DOS_PARTITION 38*320cf350SYoshihiro Shimoda #define CONFIG_MAC_PARTITION 39*320cf350SYoshihiro Shimoda 40*320cf350SYoshihiro Shimoda #define CONFIG_BAUDRATE 115200 41*320cf350SYoshihiro Shimoda #define CONFIG_BOOTDELAY 3 42*320cf350SYoshihiro Shimoda #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 43*320cf350SYoshihiro Shimoda 44*320cf350SYoshihiro Shimoda #define CONFIG_VERSION_VARIABLE 45*320cf350SYoshihiro Shimoda #undef CONFIG_SHOW_BOOT_PROGRESS 46*320cf350SYoshihiro Shimoda #define CONFIG_CMDLINE_EDITING 47*320cf350SYoshihiro Shimoda #define CONFIG_AUTO_COMPLETE 48*320cf350SYoshihiro Shimoda 49*320cf350SYoshihiro Shimoda /* MEMORY */ 50*320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_BASE (0x40000000) 51*320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) 52*320cf350SYoshihiro Shimoda 53*320cf350SYoshihiro Shimoda #define CONFIG_SYS_LONGHELP 54*320cf350SYoshihiro Shimoda #define CONFIG_SYS_CBSIZE 256 55*320cf350SYoshihiro Shimoda #define CONFIG_SYS_PBSIZE 256 56*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MAXARGS 16 57*320cf350SYoshihiro Shimoda #define CONFIG_SYS_BARGSIZE 512 58*320cf350SYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 59*320cf350SYoshihiro Shimoda 60*320cf350SYoshihiro Shimoda /* SCIF */ 61*320cf350SYoshihiro Shimoda #define CONFIG_SCIF_CONSOLE 1 62*320cf350SYoshihiro Shimoda #define CONFIG_CONS_SCIF2 1 63*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_INFO_QUIET 64*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 65*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 66*320cf350SYoshihiro Shimoda 67*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) 68*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 69*320cf350SYoshihiro Shimoda 480 * 1024 * 1024) 70*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_ALT_MEMTEST 71*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_MEMTEST_SCRATCH 72*320cf350SYoshihiro Shimoda #undef CONFIG_SYS_LOADS_BAUD_CHANGE 73*320cf350SYoshihiro Shimoda 74*320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) 75*320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) 76*320cf350SYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 77*320cf350SYoshihiro Shimoda 128 * 1024 * 1024) 78*320cf350SYoshihiro Shimoda 79*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE 0x00000000 80*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 81*320cf350SYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 82*320cf350SYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 83*320cf350SYoshihiro Shimoda 84*320cf350SYoshihiro Shimoda /* FLASH */ 85*320cf350SYoshihiro Shimoda #define CONFIG_SYS_NO_FLASH 86*320cf350SYoshihiro Shimoda 87*320cf350SYoshihiro Shimoda /* Ether */ 88*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER 1 89*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT 0 90*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR 18 91*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 92*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER 1 93*320cf350SYoshihiro Shimoda #define CONFIG_PHYLIB 94*320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII 95*320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI 96*320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII 97*320cf350SYoshihiro Shimoda #define CONFIG_PHY_VITESSE 98*320cf350SYoshihiro Shimoda 99*320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 100*320cf350SYoshihiro Shimoda #define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) 101*320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI 102*320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_SIZE 17 103*320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_NUM_CH 2 104*320cf350SYoshihiro Shimoda #define CONFIG_BOARD_LATE_INIT 105*320cf350SYoshihiro Shimoda 106*320cf350SYoshihiro Shimoda /* SPI */ 107*320cf350SYoshihiro Shimoda #define CONFIG_SH_SPI 1 108*320cf350SYoshihiro Shimoda #define CONFIG_SH_SPI_BASE 0xfe002000 109*320cf350SYoshihiro Shimoda #define CONFIG_SPI_FLASH 110*320cf350SYoshihiro Shimoda #define CONFIG_SPI_FLASH_STMICRO 1 111*320cf350SYoshihiro Shimoda #define CONFIG_SPI_FLASH_MACRONIX 1 112*320cf350SYoshihiro Shimoda 113*320cf350SYoshihiro Shimoda /* MMCIF */ 114*320cf350SYoshihiro Shimoda #define CONFIG_MMC 1 115*320cf350SYoshihiro Shimoda #define CONFIG_GENERIC_MMC 1 116*320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF 1 117*320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 118*320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK 48000000 119*320cf350SYoshihiro Shimoda 120*320cf350SYoshihiro Shimoda /* ENV setting */ 121*320cf350SYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED 122*320cf350SYoshihiro Shimoda #define CONFIG_ENV_IS_IN_SPI_FLASH 123*320cf350SYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE (64 * 1024) 124*320cf350SYoshihiro Shimoda #define CONFIG_ENV_ADDR (0x00080000) 125*320cf350SYoshihiro Shimoda #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 126*320cf350SYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE 1 127*320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 128*320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 129*320cf350SYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS \ 130*320cf350SYoshihiro Shimoda "netboot=bootp; bootm\0" 131*320cf350SYoshihiro Shimoda 132*320cf350SYoshihiro Shimoda /* Board Clock */ 133*320cf350SYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ 48000000 134*320cf350SYoshihiro Shimoda #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 135*320cf350SYoshihiro Shimoda #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 136*320cf350SYoshihiro Shimoda #define CONFIG_SYS_TMU_CLK_DIV 4 137*320cf350SYoshihiro Shimoda #endif /* __SH7753EVB_H */ 138