1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2320cf350SYoshihiro Shimoda /* 3320cf350SYoshihiro Shimoda * Configuation settings for the sh7753evb board 4320cf350SYoshihiro Shimoda * 5320cf350SYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 6320cf350SYoshihiro Shimoda */ 7320cf350SYoshihiro Shimoda 8320cf350SYoshihiro Shimoda #ifndef __SH7753EVB_H 9320cf350SYoshihiro Shimoda #define __SH7753EVB_H 10320cf350SYoshihiro Shimoda 11320cf350SYoshihiro Shimoda #define CONFIG_CPU_SH7753 1 12320cf350SYoshihiro Shimoda 1318a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 14320cf350SYoshihiro Shimoda #undef CONFIG_SHOW_BOOT_PROGRESS 15320cf350SYoshihiro Shimoda 16320cf350SYoshihiro Shimoda /* MEMORY */ 17320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_BASE (0x40000000) 18320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) 19320cf350SYoshihiro Shimoda 20320cf350SYoshihiro Shimoda #define CONFIG_SYS_PBSIZE 256 21320cf350SYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 22320cf350SYoshihiro Shimoda 23320cf350SYoshihiro Shimoda /* SCIF */ 24320cf350SYoshihiro Shimoda #define CONFIG_CONS_SCIF2 1 25320cf350SYoshihiro Shimoda 26320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) 27320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 28320cf350SYoshihiro Shimoda 480 * 1024 * 1024) 29320cf350SYoshihiro Shimoda #undef CONFIG_SYS_MEMTEST_SCRATCH 30320cf350SYoshihiro Shimoda #undef CONFIG_SYS_LOADS_BAUD_CHANGE 31320cf350SYoshihiro Shimoda 32320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) 33320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) 34320cf350SYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 35320cf350SYoshihiro Shimoda 128 * 1024 * 1024) 36320cf350SYoshihiro Shimoda 37320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE 0x00000000 38320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 39320cf350SYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 40320cf350SYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 41320cf350SYoshihiro Shimoda 42320cf350SYoshihiro Shimoda /* Ether */ 43320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT 0 44320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR 18 45320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 46320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER 1 47320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII 48320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI 49320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII 50320cf350SYoshihiro Shimoda #define CONFIG_PHY_VITESSE 51320cf350SYoshihiro Shimoda 52320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 53320cf350SYoshihiro Shimoda #define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) 54320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI 55320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_SIZE 17 56320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_NUM_CH 2 57320cf350SYoshihiro Shimoda 58320cf350SYoshihiro Shimoda /* SPI */ 59320cf350SYoshihiro Shimoda #define CONFIG_SH_SPI_BASE 0xfe002000 60320cf350SYoshihiro Shimoda 61320cf350SYoshihiro Shimoda /* MMCIF */ 62320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 63320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK 48000000 64320cf350SYoshihiro Shimoda 65320cf350SYoshihiro Shimoda /* ENV setting */ 66320cf350SYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED 67320cf350SYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE (64 * 1024) 68320cf350SYoshihiro Shimoda #define CONFIG_ENV_ADDR (0x00080000) 69320cf350SYoshihiro Shimoda #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 70320cf350SYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE 1 71320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 72320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 73320cf350SYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS \ 74320cf350SYoshihiro Shimoda "netboot=bootp; bootm\0" 75320cf350SYoshihiro Shimoda 76320cf350SYoshihiro Shimoda /* Board Clock */ 77320cf350SYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ 48000000 78320cf350SYoshihiro Shimoda #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 79320cf350SYoshihiro Shimoda #endif /* __SH7753EVB_H */ 80