1ee4bbbcbSTom Warren /* 2ee4bbbcbSTom Warren * (C) Copyright 2010,2011 3ee4bbbcbSTom Warren * NVIDIA Corporation <www.nvidia.com> 4ee4bbbcbSTom Warren * 5ee4bbbcbSTom Warren * See file CREDITS for list of people who contributed to this 6ee4bbbcbSTom Warren * project. 7ee4bbbcbSTom Warren * 8ee4bbbcbSTom Warren * This program is free software; you can redistribute it and/or 9ee4bbbcbSTom Warren * modify it under the terms of the GNU General Public License as 10ee4bbbcbSTom Warren * published by the Free Software Foundation; either version 2 of 11ee4bbbcbSTom Warren * the License, or (at your option) any later version. 12ee4bbbcbSTom Warren * 13ee4bbbcbSTom Warren * This program is distributed in the hope that it will be useful, 14ee4bbbcbSTom Warren * but WITHOUT ANY WARRANTY; without even the implied warranty of 15ee4bbbcbSTom Warren * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ee4bbbcbSTom Warren * GNU General Public License for more details. 17ee4bbbcbSTom Warren * 18ee4bbbcbSTom Warren * You should have received a copy of the GNU General Public License 19ee4bbbcbSTom Warren * along with this program; if not, write to the Free Software 20ee4bbbcbSTom Warren * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21ee4bbbcbSTom Warren * MA 02111-1307 USA 22ee4bbbcbSTom Warren */ 23ee4bbbcbSTom Warren 24ee4bbbcbSTom Warren #ifndef __CONFIG_H 25ee4bbbcbSTom Warren #define __CONFIG_H 26ee4bbbcbSTom Warren 27ee4bbbcbSTom Warren #include <asm/sizes.h> 28649d0ffbSSimon Glass 29649d0ffbSSimon Glass /* LP0 suspend / resume */ 3029f3e3f2STom Warren #define CONFIG_TEGRA_LP0 31649d0ffbSSimon Glass #define CONFIG_AES 32649d0ffbSSimon Glass #define CONFIG_TEGRA_PMU 33649d0ffbSSimon Glass #define CONFIG_TPS6586X_POWER 34649d0ffbSSimon Glass #define CONFIG_TEGRA_CLOCK_SCALING 35649d0ffbSSimon Glass 3600a2749dSAllen Martin #include "tegra20-common.h" 37ee4bbbcbSTom Warren 38d9fdfe0aSSimon Glass /* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ 3900a2749dSAllen Martin #define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard 40d9fdfe0aSSimon Glass #define CONFIG_OF_CONTROL 41d9fdfe0aSSimon Glass #define CONFIG_OF_SEPARATE 42d9fdfe0aSSimon Glass 43ee4bbbcbSTom Warren /* High-level configuration options */ 4400a2749dSAllen Martin #define V_PROMPT "Tegra20 (SeaBoard) # " 4529f3e3f2STom Warren #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" 46ee4bbbcbSTom Warren 47ee4bbbcbSTom Warren /* Board-specific serial config */ 4829f3e3f2STom Warren #define CONFIG_TEGRA_ENABLE_UARTD 49ee4bbbcbSTom Warren #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE 50ee4bbbcbSTom Warren 51bf80088aSSimon Glass /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ 52bf80088aSSimon Glass #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 53bf80088aSSimon Glass 5405858736STom Warren #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD 55ee4bbbcbSTom Warren 5674652cf6STom Warren #define CONFIG_BOARD_EARLY_INIT_F 5783800959STom Warren 58905fe99bSSimon Glass /* I2C */ 59905fe99bSSimon Glass #define CONFIG_TEGRA_I2C 60905fe99bSSimon Glass #define CONFIG_SYS_I2C_INIT_BOARD 61905fe99bSSimon Glass #define CONFIG_I2C_MULTI_BUS 62905fe99bSSimon Glass #define CONFIG_SYS_MAX_I2C_BUS 4 63905fe99bSSimon Glass #define CONFIG_SYS_I2C_SPEED 100000 64905fe99bSSimon Glass #define CONFIG_CMD_I2C 65905fe99bSSimon Glass 6683800959STom Warren /* SD/MMC */ 6783800959STom Warren #define CONFIG_MMC 6883800959STom Warren #define CONFIG_GENERIC_MMC 693f82d89dSTom Warren #define CONFIG_TEGRA_MMC 7083800959STom Warren #define CONFIG_CMD_MMC 7183800959STom Warren 7283800959STom Warren #define CONFIG_DOS_PARTITION 7383800959STom Warren #define CONFIG_EFI_PARTITION 7483800959STom Warren #define CONFIG_CMD_EXT2 7583800959STom Warren #define CONFIG_CMD_FAT 769dd79fdbSSimon Glass 77f9f2f12eSStephen Warren /* Environment in eMMC, at the end of 2nd "boot sector" */ 78f9f2f12eSStephen Warren #define CONFIG_ENV_IS_IN_MMC 79573668a2SStephen Warren #define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) 80f9f2f12eSStephen Warren #define CONFIG_SYS_MMC_ENV_DEV 0 81573668a2SStephen Warren #define CONFIG_SYS_MMC_ENV_PART 2 82db44ebdbSSimon Glass 83db44ebdbSSimon Glass /* USB Host support */ 84e73c7cddSStephen Warren #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 85db44ebdbSSimon Glass #define CONFIG_USB_EHCI 86db44ebdbSSimon Glass #define CONFIG_USB_EHCI_TEGRA 87db44ebdbSSimon Glass #define CONFIG_USB_STORAGE 88db44ebdbSSimon Glass #define CONFIG_CMD_USB 89db44ebdbSSimon Glass 90defd5e49SStephen Warren /* USB networking support */ 91defd5e49SStephen Warren #define CONFIG_USB_HOST_ETHER 92defd5e49SStephen Warren #define CONFIG_USB_ETHER_ASIX 93defd5e49SStephen Warren 94defd5e49SStephen Warren /* General networking support */ 95defd5e49SStephen Warren #define CONFIG_CMD_NET 96defd5e49SStephen Warren #define CONFIG_CMD_DHCP 97defd5e49SStephen Warren 982cacf516SSimon Glass /* Enable keyboard */ 9929f3e3f2STom Warren #define CONFIG_TEGRA_KEYBOARD 1002cacf516SSimon Glass #define CONFIG_KEYBOARD 1012cacf516SSimon Glass 102*5ddcc38bSAllen Martin /* USB keyboard */ 103*5ddcc38bSAllen Martin #define CONFIG_USB_KEYBOARD 104*5ddcc38bSAllen Martin 10529f3e3f2STom Warren #include "tegra-common-post.h" 106bea2674cSStephen Warren 1070dd84084SSimon Glass /* NAND support */ 1080dd84084SSimon Glass #define CONFIG_CMD_NAND 1090dd84084SSimon Glass #define CONFIG_TEGRA_NAND 1100dd84084SSimon Glass 1110dd84084SSimon Glass /* Max number of NAND devices */ 1120dd84084SSimon Glass #define CONFIG_SYS_MAX_NAND_DEVICE 1 1130dd84084SSimon Glass 1140dd84084SSimon Glass /* Somewhat oddly, the NAND base address must be a config option */ 11529f3e3f2STom Warren #define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE 116ee4bbbcbSTom Warren #endif /* __CONFIG_H */ 117