1ee4bbbcbSTom Warren /* 2ee4bbbcbSTom Warren * (C) Copyright 2010,2011 3ee4bbbcbSTom Warren * NVIDIA Corporation <www.nvidia.com> 4ee4bbbcbSTom Warren * 5ee4bbbcbSTom Warren * See file CREDITS for list of people who contributed to this 6ee4bbbcbSTom Warren * project. 7ee4bbbcbSTom Warren * 8ee4bbbcbSTom Warren * This program is free software; you can redistribute it and/or 9ee4bbbcbSTom Warren * modify it under the terms of the GNU General Public License as 10ee4bbbcbSTom Warren * published by the Free Software Foundation; either version 2 of 11ee4bbbcbSTom Warren * the License, or (at your option) any later version. 12ee4bbbcbSTom Warren * 13ee4bbbcbSTom Warren * This program is distributed in the hope that it will be useful, 14ee4bbbcbSTom Warren * but WITHOUT ANY WARRANTY; without even the implied warranty of 15ee4bbbcbSTom Warren * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ee4bbbcbSTom Warren * GNU General Public License for more details. 17ee4bbbcbSTom Warren * 18ee4bbbcbSTom Warren * You should have received a copy of the GNU General Public License 19ee4bbbcbSTom Warren * along with this program; if not, write to the Free Software 20ee4bbbcbSTom Warren * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21ee4bbbcbSTom Warren * MA 02111-1307 USA 22ee4bbbcbSTom Warren */ 23ee4bbbcbSTom Warren 24ee4bbbcbSTom Warren #ifndef __CONFIG_H 25ee4bbbcbSTom Warren #define __CONFIG_H 26ee4bbbcbSTom Warren 27ee4bbbcbSTom Warren #include <asm/sizes.h> 28649d0ffbSSimon Glass 29649d0ffbSSimon Glass /* LP0 suspend / resume */ 30649d0ffbSSimon Glass #define CONFIG_TEGRA2_LP0 31649d0ffbSSimon Glass #define CONFIG_AES 32649d0ffbSSimon Glass #define CONFIG_TEGRA_PMU 33649d0ffbSSimon Glass #define CONFIG_TPS6586X_POWER 34649d0ffbSSimon Glass #define CONFIG_TEGRA_CLOCK_SCALING 35649d0ffbSSimon Glass 36ee4bbbcbSTom Warren #include "tegra2-common.h" 37ee4bbbcbSTom Warren 38d9fdfe0aSSimon Glass /* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ 39d9fdfe0aSSimon Glass #define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard 40d9fdfe0aSSimon Glass #define CONFIG_OF_CONTROL 41d9fdfe0aSSimon Glass #define CONFIG_OF_SEPARATE 42d9fdfe0aSSimon Glass 43ee4bbbcbSTom Warren /* High-level configuration options */ 44ee4bbbcbSTom Warren #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" 45ee4bbbcbSTom Warren #define V_PROMPT "Tegra2 (SeaBoard) # " 46ee4bbbcbSTom Warren #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard" 47ee4bbbcbSTom Warren 48ee4bbbcbSTom Warren /* Board-specific serial config */ 49ee4bbbcbSTom Warren #define CONFIG_SERIAL_MULTI 50ee4bbbcbSTom Warren #define CONFIG_TEGRA2_ENABLE_UARTD 51ee4bbbcbSTom Warren #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE 52ee4bbbcbSTom Warren 53bf80088aSSimon Glass /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ 54bf80088aSSimon Glass #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 55*046c76a6STom Warren /* 56*046c76a6STom Warren * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are 57*046c76a6STom Warren * needed to work around that design error. 58*046c76a6STom Warren */ 59*046c76a6STom Warren #define CONFIG_SPI_UART_SWITCH 60*046c76a6STom Warren #define CONFIG_SPI_CORRUPTS_UART NV_PA_APB_UARTD_BASE 61*046c76a6STom Warren #define CONFIG_SPI_CORRUPTS_UART_NR 3 62*046c76a6STom Warren #define CONFIG_SPI_CORRUPTS_UART_DLY 2500 63*046c76a6STom Warren #undef CONFIG_CMDLINE_EDITING /* avoid NUL in input buffer */ 64bf80088aSSimon Glass 6505858736STom Warren #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD 66ee4bbbcbSTom Warren #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ 67ee4bbbcbSTom Warren 6874652cf6STom Warren #define CONFIG_BOARD_EARLY_INIT_F 6983800959STom Warren 70bf80088aSSimon Glass /* SPI */ 71bf80088aSSimon Glass #define CONFIG_TEGRA2_SPI 72bf80088aSSimon Glass #define CONFIG_SPI_FLASH 73bf80088aSSimon Glass #define CONFIG_SPI_FLASH_WINBOND 74bf80088aSSimon Glass #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 75bf80088aSSimon Glass #define CONFIG_CMD_SPI 76bf80088aSSimon Glass #define CONFIG_CMD_SF 779dd79fdbSSimon Glass #define CONFIG_SPI_FLASH_SIZE (4 << 20) 78bf80088aSSimon Glass 79905fe99bSSimon Glass /* I2C */ 80905fe99bSSimon Glass #define CONFIG_TEGRA_I2C 81905fe99bSSimon Glass #define CONFIG_SYS_I2C_INIT_BOARD 82905fe99bSSimon Glass #define CONFIG_I2C_MULTI_BUS 83905fe99bSSimon Glass #define CONFIG_SYS_MAX_I2C_BUS 4 84905fe99bSSimon Glass #define CONFIG_SYS_I2C_SPEED 100000 85905fe99bSSimon Glass #define CONFIG_CMD_I2C 86905fe99bSSimon Glass 8783800959STom Warren /* SD/MMC */ 8883800959STom Warren #define CONFIG_MMC 8983800959STom Warren #define CONFIG_GENERIC_MMC 9083800959STom Warren #define CONFIG_TEGRA2_MMC 9183800959STom Warren #define CONFIG_CMD_MMC 9283800959STom Warren 9383800959STom Warren #define CONFIG_DOS_PARTITION 9483800959STom Warren #define CONFIG_EFI_PARTITION 9583800959STom Warren #define CONFIG_CMD_EXT2 9683800959STom Warren #define CONFIG_CMD_FAT 979dd79fdbSSimon Glass 989dd79fdbSSimon Glass /* Environment in SPI */ 999dd79fdbSSimon Glass #define CONFIG_ENV_IS_IN_SPI_FLASH 1009dd79fdbSSimon Glass #define CONFIG_ENV_SPI_MAX_HZ 48000000 1019dd79fdbSSimon Glass #define CONFIG_ENV_SPI_MODE SPI_MODE_0 1029dd79fdbSSimon Glass 1039dd79fdbSSimon Glass #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 1049dd79fdbSSimon Glass #define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) 105db44ebdbSSimon Glass 106db44ebdbSSimon Glass /* USB Host support */ 107db44ebdbSSimon Glass #define CONFIG_USB_EHCI 108db44ebdbSSimon Glass #define CONFIG_USB_EHCI_TEGRA 109db44ebdbSSimon Glass #define CONFIG_USB_STORAGE 110db44ebdbSSimon Glass #define CONFIG_CMD_USB 111db44ebdbSSimon Glass 1122cacf516SSimon Glass /* Enable keyboard */ 1132cacf516SSimon Glass #define CONFIG_TEGRA2_KEYBOARD 1142cacf516SSimon Glass #define CONFIG_KEYBOARD 1152cacf516SSimon Glass 1162cacf516SSimon Glass #undef TEGRA2_DEVICE_SETTINGS 1172cacf516SSimon Glass #define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ 1182cacf516SSimon Glass "stdout=serial\0" \ 1192cacf516SSimon Glass "stderr=serial\0" 120ee4bbbcbSTom Warren #endif /* __CONFIG_H */ 121