1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 25 #define CONFIG_MP 1 /* support multiple processors */ 26 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 27 28 #define CONFIG_SYS_TEXT_BASE 0xfff00000 29 30 #ifdef RUN_DIAG 31 #define CONFIG_SYS_DIAG_ADDR 0xff800000 32 #endif 33 34 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 35 36 /* 37 * virtual address to be used for temporary mappings. There 38 * should be 128k free at this VA. 39 */ 40 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 41 42 #define CONFIG_SYS_SRIO 43 #define CONFIG_SRIO1 /* SRIO port 1 */ 44 45 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 46 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 54 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 55 56 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 57 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 #define CACHE_LINE_INTERLEAVING 0x20000000 61 #define PAGE_INTERLEAVING 0x21000000 62 #define BANK_INTERLEAVING 0x22000000 63 #define SUPER_BANK_INTERLEAVING 0x23000000 64 65 #define CONFIG_ALTIVEC 1 66 67 /* 68 * L2CR setup -- make sure this is right for your board! 69 */ 70 #define CONFIG_SYS_L2 71 #define L2_INIT 0 72 #define L2_ENABLE (L2CR_L2E) 73 74 #ifndef CONFIG_SYS_CLK_FREQ 75 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 76 #endif 77 78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 79 80 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 82 #define CONFIG_SYS_MEMTEST_END 0x00400000 83 84 /* 85 * Base addresses -- Note these are effective addresses where the 86 * actual resources get mapped (not physical addresses) 87 */ 88 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 89 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 90 91 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 92 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 93 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 94 95 /* 96 * DDR Setup 97 */ 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 99 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 102 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 103 #define CONFIG_VERY_BIG_RAM 104 105 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 106 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 107 108 #if defined(CONFIG_SPD_EEPROM) 109 /* 110 * Determine DDR configuration from I2C interface. 111 */ 112 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 113 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 114 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 115 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 116 117 #else 118 /* 119 * Manually set up DDR1 & DDR2 parameters 120 */ 121 122 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 123 124 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 125 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 126 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 127 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 128 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 129 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 130 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 131 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 132 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 133 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 134 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 135 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 136 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 137 #define CONFIG_SYS_DDR_CFG_2 0x24401000 138 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 139 #define CONFIG_SYS_DDR_MODE_2 0x00000000 140 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 141 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 142 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 143 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 144 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 145 146 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 147 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 148 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 149 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 150 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 151 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 152 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 153 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 154 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 155 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 156 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 157 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 158 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 159 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 160 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 161 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 162 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 163 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 164 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 165 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 166 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 167 168 #endif 169 170 /* #define CONFIG_ID_EEPROM 1 171 #define ID_EEPROM_ADDR 0x57 */ 172 173 /* 174 * The SBC8641D contains 16MB flash space at ff000000. 175 */ 176 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 177 178 /* Flash */ 179 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 180 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 181 182 /* 64KB EEPROM */ 183 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 184 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 185 186 /* EPLD - User switches, board id, LEDs */ 187 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 188 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 189 190 /* Local bus SDRAM 128MB */ 191 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 192 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 193 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 194 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 195 196 /* Disk on Chip (DOC) 128MB */ 197 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 198 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 199 200 /* LCD */ 201 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 202 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 203 204 /* Control logic & misc peripherals */ 205 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 206 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 210 211 #undef CONFIG_SYS_FLASH_CHECKSUM 212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 215 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 216 217 #define CONFIG_FLASH_CFI_DRIVER 218 #define CONFIG_SYS_FLASH_CFI 219 #define CONFIG_SYS_WRITE_SWAPPED_DATA 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_PROTECTION 222 223 #undef CONFIG_CLOCKS_IN_MHZ 224 225 #define CONFIG_SYS_INIT_RAM_LOCK 1 226 #ifndef CONFIG_SYS_INIT_RAM_LOCK 227 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 228 #else 229 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 230 #endif 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 232 233 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 234 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 235 236 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 237 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 238 239 /* Serial Port */ 240 #define CONFIG_CONS_INDEX 1 241 #define CONFIG_SYS_NS16550_SERIAL 242 #define CONFIG_SYS_NS16550_REG_SIZE 1 243 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 244 245 #define CONFIG_SYS_BAUDRATE_TABLE \ 246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 247 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 250 251 /* 252 * I2C 253 */ 254 #define CONFIG_SYS_I2C 255 #define CONFIG_SYS_I2C_FSL 256 #define CONFIG_SYS_FSL_I2C_SPEED 400000 257 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 258 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 259 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 260 261 /* 262 * RapidIO MMU 263 */ 264 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 265 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 266 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 267 268 /* 269 * General PCI 270 * Addresses are mapped 1-1. 271 */ 272 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 273 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 274 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 275 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 276 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 277 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 278 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 279 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 280 281 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 282 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 283 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 284 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 285 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 286 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 287 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 288 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 289 290 #if defined(CONFIG_PCI) 291 292 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 293 294 #undef CONFIG_EEPRO100 295 #undef CONFIG_TULIP 296 297 #if !defined(CONFIG_PCI_PNP) 298 #define PCI_ENET0_IOADDR 0xe0000000 299 #define PCI_ENET0_MEMADDR 0xe0000000 300 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 301 #endif 302 303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 304 305 #define CONFIG_DOS_PARTITION 306 #undef CONFIG_SCSI_AHCI 307 308 #ifdef CONFIG_SCSI_AHCI 309 #define CONFIG_SATA_ULI5288 310 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 311 #define CONFIG_SYS_SCSI_MAX_LUN 1 312 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 313 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 314 #endif 315 316 #endif /* CONFIG_PCI */ 317 318 #if defined(CONFIG_TSEC_ENET) 319 320 /* #define CONFIG_MII 1 */ /* MII PHY management */ 321 322 #define CONFIG_TSEC1 1 323 #define CONFIG_TSEC1_NAME "eTSEC1" 324 #define CONFIG_TSEC2 1 325 #define CONFIG_TSEC2_NAME "eTSEC2" 326 #define CONFIG_TSEC3 1 327 #define CONFIG_TSEC3_NAME "eTSEC3" 328 #define CONFIG_TSEC4 1 329 #define CONFIG_TSEC4_NAME "eTSEC4" 330 331 #define TSEC1_PHY_ADDR 0x1F 332 #define TSEC2_PHY_ADDR 0x00 333 #define TSEC3_PHY_ADDR 0x01 334 #define TSEC4_PHY_ADDR 0x02 335 #define TSEC1_PHYIDX 0 336 #define TSEC2_PHYIDX 0 337 #define TSEC3_PHYIDX 0 338 #define TSEC4_PHYIDX 0 339 #define TSEC1_FLAGS TSEC_GIGABIT 340 #define TSEC2_FLAGS TSEC_GIGABIT 341 #define TSEC3_FLAGS TSEC_GIGABIT 342 #define TSEC4_FLAGS TSEC_GIGABIT 343 344 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 345 346 #define CONFIG_ETHPRIME "eTSEC1" 347 348 #endif /* CONFIG_TSEC_ENET */ 349 350 /* 351 * BAT0 2G Cacheable, non-guarded 352 * 0x0000_0000 2G DDR 353 */ 354 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 355 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 356 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 357 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 358 359 /* 360 * BAT1 1G Cache-inhibited, guarded 361 * 0x8000_0000 512M PCI-Express 1 Memory 362 * 0xa000_0000 512M PCI-Express 2 Memory 363 * Changed it for operating from 0xd0000000 364 */ 365 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 366 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 368 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 369 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 370 371 /* 372 * BAT2 512M Cache-inhibited, guarded 373 * 0xc000_0000 512M RapidIO Memory 374 */ 375 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 376 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 377 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 379 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 380 381 /* 382 * BAT3 4M Cache-inhibited, guarded 383 * 0xf800_0000 4M CCSR 384 */ 385 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 386 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 387 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 388 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 389 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 390 391 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 392 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 393 | BATL_PP_RW | BATL_CACHEINHIBIT \ 394 | BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 396 | BATU_BL_1M | BATU_VS | BATU_VP) 397 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 398 | BATL_PP_RW | BATL_CACHEINHIBIT) 399 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 400 #endif 401 402 /* 403 * BAT4 32M Cache-inhibited, guarded 404 * 0xe200_0000 16M PCI-Express 1 I/O 405 * 0xe300_0000 16M PCI-Express 2 I/0 406 * Note that this is at 0xe0000000 407 */ 408 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 409 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 410 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 411 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 412 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 413 414 /* 415 * BAT5 128K Cacheable, non-guarded 416 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 417 */ 418 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 419 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 421 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 422 423 /* 424 * BAT6 32M Cache-inhibited, guarded 425 * 0xfe00_0000 32M FLASH 426 */ 427 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 428 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 429 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 430 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 431 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 432 433 /* Map the last 1M of flash where we're running from reset */ 434 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 435 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 438 | BATL_MEMCOHERENCE) 439 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 440 441 #define CONFIG_SYS_DBAT7L 0x00000000 442 #define CONFIG_SYS_DBAT7U 0x00000000 443 #define CONFIG_SYS_IBAT7L 0x00000000 444 #define CONFIG_SYS_IBAT7U 0x00000000 445 446 /* 447 * Environment 448 */ 449 #define CONFIG_ENV_IS_IN_FLASH 1 450 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 451 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 452 #define CONFIG_ENV_SIZE 0x2000 453 454 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 455 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 456 457 #define CONFIG_CMD_REGINFO 458 459 #if defined(CONFIG_PCI) 460 #define CONFIG_CMD_PCI 461 #endif 462 463 #undef CONFIG_WATCHDOG /* watchdog disabled */ 464 465 /* 466 * Miscellaneous configurable options 467 */ 468 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 469 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 470 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 471 472 #if defined(CONFIG_CMD_KGDB) 473 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 474 #else 475 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 476 #endif 477 478 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 479 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 480 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 481 482 /* 483 * For booting Linux, the board info and command line data 484 * have to be in the first 8 MB of memory, since this is 485 * the maximum mapped by the Linux kernel during initialization. 486 */ 487 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 488 489 /* Cache Configuration */ 490 #define CONFIG_SYS_DCACHE_SIZE 32768 491 #define CONFIG_SYS_CACHELINE_SIZE 32 492 #if defined(CONFIG_CMD_KGDB) 493 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 494 #endif 495 496 #if defined(CONFIG_CMD_KGDB) 497 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 498 #endif 499 500 /* 501 * Environment Configuration 502 */ 503 504 #define CONFIG_HAS_ETH0 1 505 #define CONFIG_HAS_ETH1 1 506 #define CONFIG_HAS_ETH2 1 507 #define CONFIG_HAS_ETH3 1 508 509 #define CONFIG_IPADDR 192.168.0.50 510 511 #define CONFIG_HOSTNAME sbc8641d 512 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 513 #define CONFIG_BOOTFILE "uImage" 514 515 #define CONFIG_SERVERIP 192.168.0.2 516 #define CONFIG_GATEWAYIP 192.168.0.1 517 #define CONFIG_NETMASK 255.255.255.0 518 519 /* default location for tftp and bootm */ 520 #define CONFIG_LOADADDR 1000000 521 522 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 523 524 #define CONFIG_BAUDRATE 115200 525 526 #define CONFIG_EXTRA_ENV_SETTINGS \ 527 "netdev=eth0\0" \ 528 "consoledev=ttyS0\0" \ 529 "ramdiskaddr=2000000\0" \ 530 "ramdiskfile=uRamdisk\0" \ 531 "dtbaddr=400000\0" \ 532 "dtbfile=sbc8641d.dtb\0" \ 533 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 534 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 535 "maxcpus=1" 536 537 #define CONFIG_NFSBOOTCOMMAND \ 538 "setenv bootargs root=/dev/nfs rw " \ 539 "nfsroot=$serverip:$rootpath " \ 540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 541 "console=$consoledev,$baudrate $othbootargs;" \ 542 "tftp $loadaddr $bootfile;" \ 543 "tftp $dtbaddr $dtbfile;" \ 544 "bootm $loadaddr - $dtbaddr" 545 546 #define CONFIG_RAMBOOTCOMMAND \ 547 "setenv bootargs root=/dev/ram rw " \ 548 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 549 "console=$consoledev,$baudrate $othbootargs;" \ 550 "tftp $ramdiskaddr $ramdiskfile;" \ 551 "tftp $loadaddr $bootfile;" \ 552 "tftp $dtbaddr $dtbfile;" \ 553 "bootm $loadaddr $ramdiskaddr $dtbaddr" 554 555 #define CONFIG_FLASHBOOTCOMMAND \ 556 "setenv bootargs root=/dev/ram rw " \ 557 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 558 "console=$consoledev,$baudrate $othbootargs;" \ 559 "bootm ffd00000 ffb00000 ffa00000" 560 561 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 562 563 #endif /* __CONFIG_H */ 564