1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * SBC8641D board configuration file 31 * 32 * Make sure you change the MAC address and other network params first, 33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 34 */ 35 36 #ifndef __CONFIG_H 37 #define __CONFIG_H 38 39 /* High Level Configuration Options */ 40 #define CONFIG_MPC86xx 1 /* MPC86xx */ 41 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 43 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 44 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 45 46 #ifdef RUN_DIAG 47 #define CONFIG_SYS_DIAG_ADDR 0xff800000 48 #endif 49 50 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 51 52 /* 53 * virtual address to be used for temporary mappings. There 54 * should be 128k free at this VA. 55 */ 56 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 57 58 #define CONFIG_PCI 1 /* Enable PCIE */ 59 #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ 60 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ 61 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 62 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 63 64 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 68 69 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 70 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 #define CONFIG_NUM_DDR_CONTROLLERS 2 74 #define CACHE_LINE_INTERLEAVING 0x20000000 75 #define PAGE_INTERLEAVING 0x21000000 76 #define BANK_INTERLEAVING 0x22000000 77 #define SUPER_BANK_INTERLEAVING 0x23000000 78 79 80 #define CONFIG_ALTIVEC 1 81 82 /* 83 * L2CR setup -- make sure this is right for your board! 84 */ 85 #define CONFIG_SYS_L2 86 #define L2_INIT 0 87 #define L2_ENABLE (L2CR_L2E) 88 89 #ifndef CONFIG_SYS_CLK_FREQ 90 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 91 #endif 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 99 /* 100 * Base addresses -- Note these are effective addresses where the 101 * actual resources get mapped (not physical addresses) 102 */ 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 104 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 105 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 106 107 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 108 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 109 110 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 111 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 112 113 /* 114 * DDR Setup 115 */ 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 117 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 119 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 120 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 121 #define CONFIG_VERY_BIG_RAM 122 123 #define MPC86xx_DDR_SDRAM_CLK_CNTL 124 125 #define CONFIG_NUM_DDR_CONTROLLERS 2 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 127 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 128 129 #if defined(CONFIG_SPD_EEPROM) 130 /* 131 * Determine DDR configuration from I2C interface. 132 */ 133 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 134 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 135 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 136 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 137 138 #else 139 /* 140 * Manually set up DDR1 & DDR2 parameters 141 */ 142 143 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 144 145 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 146 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 147 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 148 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 149 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 150 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 151 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 152 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 153 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 154 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 155 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 156 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 157 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 158 #define CONFIG_SYS_DDR_CFG_2 0x24401000 159 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 160 #define CONFIG_SYS_DDR_MODE_2 0x00000000 161 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 162 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 163 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 164 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 165 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 166 167 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 168 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 169 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 170 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 171 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 172 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 173 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 174 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 175 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 176 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 177 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 178 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 179 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 180 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 181 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 182 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 183 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 184 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 185 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 186 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 187 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 188 189 190 #endif 191 192 /* #define CONFIG_ID_EEPROM 1 193 #define ID_EEPROM_ADDR 0x57 */ 194 195 /* 196 * The SBC8641D contains 16MB flash space at ff000000. 197 */ 198 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 199 200 /* Flash */ 201 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 202 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 203 204 /* 64KB EEPROM */ 205 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 206 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 207 208 /* EPLD - User switches, board id, LEDs */ 209 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 210 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 211 212 /* Local bus SDRAM 128MB */ 213 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 214 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 215 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 216 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 217 218 /* Disk on Chip (DOC) 128MB */ 219 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 220 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 221 222 /* LCD */ 223 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 224 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 225 226 /* Control logic & misc peripherals */ 227 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 228 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 229 230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 231 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 232 233 #undef CONFIG_SYS_FLASH_CHECKSUM 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 237 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 238 239 #define CONFIG_FLASH_CFI_DRIVER 240 #define CONFIG_SYS_FLASH_CFI 241 #define CONFIG_SYS_WRITE_SWAPPED_DATA 242 #define CONFIG_SYS_FLASH_EMPTY_INFO 243 #define CONFIG_SYS_FLASH_PROTECTION 244 245 #undef CONFIG_CLOCKS_IN_MHZ 246 247 #define CONFIG_SYS_INIT_RAM_LOCK 1 248 #ifndef CONFIG_SYS_INIT_RAM_LOCK 249 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 250 #else 251 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 252 #endif 253 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 254 255 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 256 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 258 259 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 260 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 261 262 /* Serial Port */ 263 #define CONFIG_CONS_INDEX 1 264 #undef CONFIG_SERIAL_SOFTWARE_FIFO 265 #define CONFIG_SYS_NS16550 266 #define CONFIG_SYS_NS16550_SERIAL 267 #define CONFIG_SYS_NS16550_REG_SIZE 1 268 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 269 270 #define CONFIG_SYS_BAUDRATE_TABLE \ 271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 272 273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 275 276 /* Use the HUSH parser */ 277 #define CONFIG_SYS_HUSH_PARSER 278 #ifdef CONFIG_SYS_HUSH_PARSER 279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 280 #endif 281 282 /* 283 * Pass open firmware flat tree to kernel 284 */ 285 #define CONFIG_OF_LIBFDT 1 286 #define CONFIG_OF_BOARD_SETUP 1 287 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 288 289 #define CONFIG_SYS_64BIT_VSPRINTF 1 290 #define CONFIG_SYS_64BIT_STRTOUL 1 291 292 /* 293 * I2C 294 */ 295 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 296 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 297 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 298 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 299 #define CONFIG_SYS_I2C_SLAVE 0x7F 300 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 301 #define CONFIG_SYS_I2C_OFFSET 0x3100 302 303 /* 304 * RapidIO MMU 305 */ 306 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ 307 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 308 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 309 310 /* 311 * General PCI 312 * Addresses are mapped 1-1. 313 */ 314 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 315 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 316 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 317 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 318 #define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 319 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS 320 #define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS 321 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 322 323 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 324 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS 325 #define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS 326 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 327 #define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 328 #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS 329 #define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS 330 #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ 331 332 #if defined(CONFIG_PCI) 333 334 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 335 336 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 337 338 #define CONFIG_NET_MULTI 339 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 340 341 #undef CONFIG_EEPRO100 342 #undef CONFIG_TULIP 343 344 #if !defined(CONFIG_PCI_PNP) 345 #define PCI_ENET0_IOADDR 0xe0000000 346 #define PCI_ENET0_MEMADDR 0xe0000000 347 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 348 #endif 349 350 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 351 352 #define CONFIG_DOS_PARTITION 353 #undef CONFIG_SCSI_AHCI 354 355 #ifdef CONFIG_SCSI_AHCI 356 #define CONFIG_SATA_ULI5288 357 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 358 #define CONFIG_SYS_SCSI_MAX_LUN 1 359 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 360 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 361 #endif 362 363 #endif /* CONFIG_PCI */ 364 365 #if defined(CONFIG_TSEC_ENET) 366 367 #ifndef CONFIG_NET_MULTI 368 #define CONFIG_NET_MULTI 1 369 #endif 370 371 /* #define CONFIG_MII 1 */ /* MII PHY management */ 372 373 #define CONFIG_TSEC1 1 374 #define CONFIG_TSEC1_NAME "eTSEC1" 375 #define CONFIG_TSEC2 1 376 #define CONFIG_TSEC2_NAME "eTSEC2" 377 #define CONFIG_TSEC3 1 378 #define CONFIG_TSEC3_NAME "eTSEC3" 379 #define CONFIG_TSEC4 1 380 #define CONFIG_TSEC4_NAME "eTSEC4" 381 382 #define TSEC1_PHY_ADDR 0x1F 383 #define TSEC2_PHY_ADDR 0x00 384 #define TSEC3_PHY_ADDR 0x01 385 #define TSEC4_PHY_ADDR 0x02 386 #define TSEC1_PHYIDX 0 387 #define TSEC2_PHYIDX 0 388 #define TSEC3_PHYIDX 0 389 #define TSEC4_PHYIDX 0 390 #define TSEC1_FLAGS TSEC_GIGABIT 391 #define TSEC2_FLAGS TSEC_GIGABIT 392 #define TSEC3_FLAGS TSEC_GIGABIT 393 #define TSEC4_FLAGS TSEC_GIGABIT 394 395 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 396 397 #define CONFIG_ETHPRIME "eTSEC1" 398 399 #endif /* CONFIG_TSEC_ENET */ 400 401 /* 402 * BAT0 2G Cacheable, non-guarded 403 * 0x0000_0000 2G DDR 404 */ 405 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 406 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 407 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 408 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 409 410 /* 411 * BAT1 1G Cache-inhibited, guarded 412 * 0x8000_0000 512M PCI-Express 1 Memory 413 * 0xa000_0000 512M PCI-Express 2 Memory 414 * Changed it for operating from 0xd0000000 415 */ 416 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 417 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 418 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 419 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 420 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 421 422 /* 423 * BAT2 512M Cache-inhibited, guarded 424 * 0xc000_0000 512M RapidIO Memory 425 */ 426 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ 427 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 428 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 429 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 430 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 431 432 /* 433 * BAT3 4M Cache-inhibited, guarded 434 * 0xf800_0000 4M CCSR 435 */ 436 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 437 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 438 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 439 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 440 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 441 442 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 443 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 444 | BATL_PP_RW | BATL_CACHEINHIBIT \ 445 | BATL_GUARDEDSTORAGE) 446 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 447 | BATU_BL_1M | BATU_VS | BATU_VP) 448 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 449 | BATL_PP_RW | BATL_CACHEINHIBIT) 450 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 451 #endif 452 453 /* 454 * BAT4 32M Cache-inhibited, guarded 455 * 0xe200_0000 16M PCI-Express 1 I/O 456 * 0xe300_0000 16M PCI-Express 2 I/0 457 * Note that this is at 0xe0000000 458 */ 459 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ 460 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 461 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 462 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 463 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 464 465 /* 466 * BAT5 128K Cacheable, non-guarded 467 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 468 */ 469 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 470 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 471 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 472 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 473 474 /* 475 * BAT6 32M Cache-inhibited, guarded 476 * 0xfe00_0000 32M FLASH 477 */ 478 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 479 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 480 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 481 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 482 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 483 484 /* Map the last 1M of flash where we're running from reset */ 485 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 486 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 487 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 488 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 489 | BATL_MEMCOHERENCE) 490 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 491 492 #define CONFIG_SYS_DBAT7L 0x00000000 493 #define CONFIG_SYS_DBAT7U 0x00000000 494 #define CONFIG_SYS_IBAT7L 0x00000000 495 #define CONFIG_SYS_IBAT7U 0x00000000 496 497 /* 498 * Environment 499 */ 500 #define CONFIG_ENV_IS_IN_FLASH 1 501 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 502 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 503 #define CONFIG_ENV_SIZE 0x2000 504 505 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 506 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 507 508 #include <config_cmd_default.h> 509 #define CONFIG_CMD_PING 510 #define CONFIG_CMD_I2C 511 #define CONFIG_CMD_REGINFO 512 513 #if defined(CONFIG_PCI) 514 #define CONFIG_CMD_PCI 515 #endif 516 517 #undef CONFIG_WATCHDOG /* watchdog disabled */ 518 519 /* 520 * Miscellaneous configurable options 521 */ 522 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 523 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 524 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 528 #else 529 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 530 #endif 531 532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 533 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 534 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 535 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 536 537 /* 538 * For booting Linux, the board info and command line data 539 * have to be in the first 8 MB of memory, since this is 540 * the maximum mapped by the Linux kernel during initialization. 541 */ 542 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 543 544 /* Cache Configuration */ 545 #define CONFIG_SYS_DCACHE_SIZE 32768 546 #define CONFIG_SYS_CACHELINE_SIZE 32 547 #if defined(CONFIG_CMD_KGDB) 548 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 549 #endif 550 551 /* 552 * Internal Definitions 553 * 554 * Boot Flags 555 */ 556 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 557 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 558 559 #if defined(CONFIG_CMD_KGDB) 560 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 561 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 562 #endif 563 564 /* 565 * Environment Configuration 566 */ 567 568 /* The mac addresses for all ethernet interface */ 569 #if defined(CONFIG_TSEC_ENET) 570 #define CONFIG_ETHADDR 02:E0:0C:00:00:01 571 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 572 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 573 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 574 #endif 575 576 #define CONFIG_HAS_ETH0 1 577 #define CONFIG_HAS_ETH1 1 578 #define CONFIG_HAS_ETH2 1 579 #define CONFIG_HAS_ETH3 1 580 581 #define CONFIG_IPADDR 192.168.0.50 582 583 #define CONFIG_HOSTNAME sbc8641d 584 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx 585 #define CONFIG_BOOTFILE uImage 586 587 #define CONFIG_SERVERIP 192.168.0.2 588 #define CONFIG_GATEWAYIP 192.168.0.1 589 #define CONFIG_NETMASK 255.255.255.0 590 591 /* default location for tftp and bootm */ 592 #define CONFIG_LOADADDR 1000000 593 594 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 595 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 596 597 #define CONFIG_BAUDRATE 115200 598 599 #define CONFIG_EXTRA_ENV_SETTINGS \ 600 "netdev=eth0\0" \ 601 "consoledev=ttyS0\0" \ 602 "ramdiskaddr=2000000\0" \ 603 "ramdiskfile=uRamdisk\0" \ 604 "dtbaddr=400000\0" \ 605 "dtbfile=sbc8641d.dtb\0" \ 606 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 607 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 608 "maxcpus=1" 609 610 #define CONFIG_NFSBOOTCOMMAND \ 611 "setenv bootargs root=/dev/nfs rw " \ 612 "nfsroot=$serverip:$rootpath " \ 613 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $loadaddr $bootfile;" \ 616 "tftp $dtbaddr $dtbfile;" \ 617 "bootm $loadaddr - $dtbaddr" 618 619 #define CONFIG_RAMBOOTCOMMAND \ 620 "setenv bootargs root=/dev/ram rw " \ 621 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 622 "console=$consoledev,$baudrate $othbootargs;" \ 623 "tftp $ramdiskaddr $ramdiskfile;" \ 624 "tftp $loadaddr $bootfile;" \ 625 "tftp $dtbaddr $dtbfile;" \ 626 "bootm $loadaddr $ramdiskaddr $dtbaddr" 627 628 #define CONFIG_FLASHBOOTCOMMAND \ 629 "setenv bootargs root=/dev/ram rw " \ 630 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 631 "console=$consoledev,$baudrate $othbootargs;" \ 632 "bootm ffd00000 ffb00000 ffa00000" 633 634 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 635 636 #endif /* __CONFIG_H */ 637