1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MP 1 /* support multiple processors */ 25 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 26 27 #define CONFIG_SYS_TEXT_BASE 0xfff00000 28 29 #ifdef RUN_DIAG 30 #define CONFIG_SYS_DIAG_ADDR 0xff800000 31 #endif 32 33 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 34 35 /* 36 * virtual address to be used for temporary mappings. There 37 * should be 128k free at this VA. 38 */ 39 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 40 41 #define CONFIG_SYS_SRIO 42 #define CONFIG_SRIO1 /* SRIO port 1 */ 43 44 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 45 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 46 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 47 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 53 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 54 55 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 56 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 57 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 58 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 59 #define CACHE_LINE_INTERLEAVING 0x20000000 60 #define PAGE_INTERLEAVING 0x21000000 61 #define BANK_INTERLEAVING 0x22000000 62 #define SUPER_BANK_INTERLEAVING 0x23000000 63 64 #define CONFIG_ALTIVEC 1 65 66 /* 67 * L2CR setup -- make sure this is right for your board! 68 */ 69 #define CONFIG_SYS_L2 70 #define L2_INIT 0 71 #define L2_ENABLE (L2CR_L2E) 72 73 #ifndef CONFIG_SYS_CLK_FREQ 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 75 #endif 76 77 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 79 #define CONFIG_SYS_MEMTEST_END 0x00400000 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 87 88 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 89 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 90 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 91 92 /* 93 * DDR Setup 94 */ 95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 96 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 98 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 99 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 100 #define CONFIG_VERY_BIG_RAM 101 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 103 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 110 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 111 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 112 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 113 114 #else 115 /* 116 * Manually set up DDR1 & DDR2 parameters 117 */ 118 119 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 120 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 122 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 123 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 124 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 125 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 126 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 127 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 128 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 129 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 130 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 131 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 132 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 133 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 134 #define CONFIG_SYS_DDR_CFG_2 0x24401000 135 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 136 #define CONFIG_SYS_DDR_MODE_2 0x00000000 137 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 138 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 139 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 140 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 141 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 142 143 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 144 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 145 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 146 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 147 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 148 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 149 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 150 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 151 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 152 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 153 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 154 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 155 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 156 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 157 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 158 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 159 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 160 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 161 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 162 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 163 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 164 165 #endif 166 167 /* #define CONFIG_ID_EEPROM 1 168 #define ID_EEPROM_ADDR 0x57 */ 169 170 /* 171 * The SBC8641D contains 16MB flash space at ff000000. 172 */ 173 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 174 175 /* Flash */ 176 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 177 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 178 179 /* 64KB EEPROM */ 180 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 181 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 182 183 /* EPLD - User switches, board id, LEDs */ 184 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 185 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 186 187 /* Local bus SDRAM 128MB */ 188 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 189 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 190 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 191 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 192 193 /* Disk on Chip (DOC) 128MB */ 194 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 195 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 196 197 /* LCD */ 198 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 199 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 200 201 /* Control logic & misc peripherals */ 202 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 203 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 207 208 #undef CONFIG_SYS_FLASH_CHECKSUM 209 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 212 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 213 214 #define CONFIG_FLASH_CFI_DRIVER 215 #define CONFIG_SYS_FLASH_CFI 216 #define CONFIG_SYS_WRITE_SWAPPED_DATA 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 #define CONFIG_SYS_FLASH_PROTECTION 219 220 #undef CONFIG_CLOCKS_IN_MHZ 221 222 #define CONFIG_SYS_INIT_RAM_LOCK 1 223 #ifndef CONFIG_SYS_INIT_RAM_LOCK 224 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 225 #else 226 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 227 #endif 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 229 230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 232 233 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 235 236 /* Serial Port */ 237 #define CONFIG_CONS_INDEX 1 238 #define CONFIG_SYS_NS16550_SERIAL 239 #define CONFIG_SYS_NS16550_REG_SIZE 1 240 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 241 242 #define CONFIG_SYS_BAUDRATE_TABLE \ 243 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 244 245 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 246 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 247 248 /* 249 * I2C 250 */ 251 #define CONFIG_SYS_I2C 252 #define CONFIG_SYS_I2C_FSL 253 #define CONFIG_SYS_FSL_I2C_SPEED 400000 254 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 255 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 256 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 257 258 /* 259 * RapidIO MMU 260 */ 261 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 262 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 263 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 264 265 /* 266 * General PCI 267 * Addresses are mapped 1-1. 268 */ 269 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 270 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 271 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 272 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 273 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 274 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 275 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 276 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 277 278 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 279 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 280 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 281 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 282 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 283 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 284 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 285 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 286 287 #if defined(CONFIG_PCI) 288 289 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 290 291 #undef CONFIG_EEPRO100 292 #undef CONFIG_TULIP 293 294 #if !defined(CONFIG_PCI_PNP) 295 #define PCI_ENET0_IOADDR 0xe0000000 296 #define PCI_ENET0_MEMADDR 0xe0000000 297 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 298 #endif 299 300 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 301 302 #ifdef CONFIG_SCSI_AHCI 303 #define CONFIG_SATA_ULI5288 304 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 305 #define CONFIG_SYS_SCSI_MAX_LUN 1 306 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 307 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 308 #endif 309 310 #endif /* CONFIG_PCI */ 311 312 #if defined(CONFIG_TSEC_ENET) 313 314 /* #define CONFIG_MII 1 */ /* MII PHY management */ 315 316 #define CONFIG_TSEC1 1 317 #define CONFIG_TSEC1_NAME "eTSEC1" 318 #define CONFIG_TSEC2 1 319 #define CONFIG_TSEC2_NAME "eTSEC2" 320 #define CONFIG_TSEC3 1 321 #define CONFIG_TSEC3_NAME "eTSEC3" 322 #define CONFIG_TSEC4 1 323 #define CONFIG_TSEC4_NAME "eTSEC4" 324 325 #define TSEC1_PHY_ADDR 0x1F 326 #define TSEC2_PHY_ADDR 0x00 327 #define TSEC3_PHY_ADDR 0x01 328 #define TSEC4_PHY_ADDR 0x02 329 #define TSEC1_PHYIDX 0 330 #define TSEC2_PHYIDX 0 331 #define TSEC3_PHYIDX 0 332 #define TSEC4_PHYIDX 0 333 #define TSEC1_FLAGS TSEC_GIGABIT 334 #define TSEC2_FLAGS TSEC_GIGABIT 335 #define TSEC3_FLAGS TSEC_GIGABIT 336 #define TSEC4_FLAGS TSEC_GIGABIT 337 338 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 339 340 #define CONFIG_ETHPRIME "eTSEC1" 341 342 #endif /* CONFIG_TSEC_ENET */ 343 344 /* 345 * BAT0 2G Cacheable, non-guarded 346 * 0x0000_0000 2G DDR 347 */ 348 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 349 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 350 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 351 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 352 353 /* 354 * BAT1 1G Cache-inhibited, guarded 355 * 0x8000_0000 512M PCI-Express 1 Memory 356 * 0xa000_0000 512M PCI-Express 2 Memory 357 * Changed it for operating from 0xd0000000 358 */ 359 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 360 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 361 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 362 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 363 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 364 365 /* 366 * BAT2 512M Cache-inhibited, guarded 367 * 0xc000_0000 512M RapidIO Memory 368 */ 369 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 370 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 371 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 372 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 373 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 374 375 /* 376 * BAT3 4M Cache-inhibited, guarded 377 * 0xf800_0000 4M CCSR 378 */ 379 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 380 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 381 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 382 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 383 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 384 385 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 386 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 387 | BATL_PP_RW | BATL_CACHEINHIBIT \ 388 | BATL_GUARDEDSTORAGE) 389 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 390 | BATU_BL_1M | BATU_VS | BATU_VP) 391 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 392 | BATL_PP_RW | BATL_CACHEINHIBIT) 393 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 394 #endif 395 396 /* 397 * BAT4 32M Cache-inhibited, guarded 398 * 0xe200_0000 16M PCI-Express 1 I/O 399 * 0xe300_0000 16M PCI-Express 2 I/0 400 * Note that this is at 0xe0000000 401 */ 402 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 403 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 404 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 405 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 406 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 407 408 /* 409 * BAT5 128K Cacheable, non-guarded 410 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 411 */ 412 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 413 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 414 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 415 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 416 417 /* 418 * BAT6 32M Cache-inhibited, guarded 419 * 0xfe00_0000 32M FLASH 420 */ 421 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 422 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 423 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 424 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 425 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 426 427 /* Map the last 1M of flash where we're running from reset */ 428 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 429 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 430 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 431 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 432 | BATL_MEMCOHERENCE) 433 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 434 435 #define CONFIG_SYS_DBAT7L 0x00000000 436 #define CONFIG_SYS_DBAT7U 0x00000000 437 #define CONFIG_SYS_IBAT7L 0x00000000 438 #define CONFIG_SYS_IBAT7U 0x00000000 439 440 /* 441 * Environment 442 */ 443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 444 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 445 #define CONFIG_ENV_SIZE 0x2000 446 447 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 448 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 449 450 #undef CONFIG_WATCHDOG /* watchdog disabled */ 451 452 /* 453 * Miscellaneous configurable options 454 */ 455 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 456 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 457 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 458 459 /* 460 * For booting Linux, the board info and command line data 461 * have to be in the first 8 MB of memory, since this is 462 * the maximum mapped by the Linux kernel during initialization. 463 */ 464 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 465 466 /* Cache Configuration */ 467 #define CONFIG_SYS_DCACHE_SIZE 32768 468 #define CONFIG_SYS_CACHELINE_SIZE 32 469 #if defined(CONFIG_CMD_KGDB) 470 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 471 #endif 472 473 #if defined(CONFIG_CMD_KGDB) 474 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 475 #endif 476 477 /* 478 * Environment Configuration 479 */ 480 481 #define CONFIG_HAS_ETH0 1 482 #define CONFIG_HAS_ETH1 1 483 #define CONFIG_HAS_ETH2 1 484 #define CONFIG_HAS_ETH3 1 485 486 #define CONFIG_IPADDR 192.168.0.50 487 488 #define CONFIG_HOSTNAME sbc8641d 489 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 490 #define CONFIG_BOOTFILE "uImage" 491 492 #define CONFIG_SERVERIP 192.168.0.2 493 #define CONFIG_GATEWAYIP 192.168.0.1 494 #define CONFIG_NETMASK 255.255.255.0 495 496 /* default location for tftp and bootm */ 497 #define CONFIG_LOADADDR 1000000 498 499 #define CONFIG_EXTRA_ENV_SETTINGS \ 500 "netdev=eth0\0" \ 501 "consoledev=ttyS0\0" \ 502 "ramdiskaddr=2000000\0" \ 503 "ramdiskfile=uRamdisk\0" \ 504 "dtbaddr=400000\0" \ 505 "dtbfile=sbc8641d.dtb\0" \ 506 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 507 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 508 "maxcpus=1" 509 510 #define CONFIG_NFSBOOTCOMMAND \ 511 "setenv bootargs root=/dev/nfs rw " \ 512 "nfsroot=$serverip:$rootpath " \ 513 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 514 "console=$consoledev,$baudrate $othbootargs;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "tftp $dtbaddr $dtbfile;" \ 517 "bootm $loadaddr - $dtbaddr" 518 519 #define CONFIG_RAMBOOTCOMMAND \ 520 "setenv bootargs root=/dev/ram rw " \ 521 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "tftp $ramdiskaddr $ramdiskfile;" \ 524 "tftp $loadaddr $bootfile;" \ 525 "tftp $dtbaddr $dtbfile;" \ 526 "bootm $loadaddr $ramdiskaddr $dtbaddr" 527 528 #define CONFIG_FLASHBOOTCOMMAND \ 529 "setenv bootargs root=/dev/ram rw " \ 530 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 531 "console=$consoledev,$baudrate $othbootargs;" \ 532 "bootm ffd00000 ffb00000 ffa00000" 533 534 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 535 536 #endif /* __CONFIG_H */ 537