1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007 Wind River Systems <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Joe Hamman <joe.hamman@embeddedspecialties.com> 6 * 7 * Copyright 2006 Freescale Semiconductor. 8 * 9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 10 */ 11 12 /* 13 * SBC8641D board configuration file 14 * 15 * Make sure you change the MAC address and other network params first, 16 * search for CONFIG_SERVERIP, etc in this file. 17 */ 18 19 #ifndef __CONFIG_H 20 #define __CONFIG_H 21 22 /* High Level Configuration Options */ 23 #define CONFIG_MP 1 /* support multiple processors */ 24 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 25 26 #ifdef RUN_DIAG 27 #define CONFIG_SYS_DIAG_ADDR 0xff800000 28 #endif 29 30 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 31 32 /* 33 * virtual address to be used for temporary mappings. There 34 * should be 128k free at this VA. 35 */ 36 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 37 38 #define CONFIG_SYS_SRIO 39 #define CONFIG_SRIO1 /* SRIO port 1 */ 40 41 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 42 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 45 46 #define CONFIG_ENV_OVERWRITE 47 48 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 49 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 50 51 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 54 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 55 #define CACHE_LINE_INTERLEAVING 0x20000000 56 #define PAGE_INTERLEAVING 0x21000000 57 #define BANK_INTERLEAVING 0x22000000 58 #define SUPER_BANK_INTERLEAVING 0x23000000 59 60 #define CONFIG_ALTIVEC 1 61 62 /* 63 * L2CR setup -- make sure this is right for your board! 64 */ 65 #define CONFIG_SYS_L2 66 #define L2_INIT 0 67 #define L2_ENABLE (L2CR_L2E) 68 69 #ifndef CONFIG_SYS_CLK_FREQ 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 71 #endif 72 73 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 74 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 75 #define CONFIG_SYS_MEMTEST_END 0x00400000 76 77 /* 78 * Base addresses -- Note these are effective addresses where the 79 * actual resources get mapped (not physical addresses) 80 */ 81 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 83 84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 85 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 87 88 /* 89 * DDR Setup 90 */ 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 92 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 94 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 95 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 96 #define CONFIG_VERY_BIG_RAM 97 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 99 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 100 101 #if defined(CONFIG_SPD_EEPROM) 102 /* 103 * Determine DDR configuration from I2C interface. 104 */ 105 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 106 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 107 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 108 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 109 110 #else 111 /* 112 * Manually set up DDR1 & DDR2 parameters 113 */ 114 115 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 116 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 118 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 119 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 120 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 121 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 122 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 123 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 124 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 125 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 126 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 127 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 128 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 129 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 130 #define CONFIG_SYS_DDR_CFG_2 0x24401000 131 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 132 #define CONFIG_SYS_DDR_MODE_2 0x00000000 133 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 134 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 135 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 137 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 138 139 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 140 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 141 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 142 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 143 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 144 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 145 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 146 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 147 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 148 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 149 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 150 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 151 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 152 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 153 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 154 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 155 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 156 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 157 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 158 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 159 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 160 161 #endif 162 163 /* #define CONFIG_ID_EEPROM 1 164 #define ID_EEPROM_ADDR 0x57 */ 165 166 /* 167 * The SBC8641D contains 16MB flash space at ff000000. 168 */ 169 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 170 171 /* Flash */ 172 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 173 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 174 175 /* 64KB EEPROM */ 176 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 177 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 178 179 /* EPLD - User switches, board id, LEDs */ 180 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 181 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 182 183 /* Local bus SDRAM 128MB */ 184 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 185 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 186 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 187 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 188 189 /* Disk on Chip (DOC) 128MB */ 190 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 191 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 192 193 /* LCD */ 194 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 195 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 196 197 /* Control logic & misc peripherals */ 198 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 199 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 200 201 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 202 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 203 204 #undef CONFIG_SYS_FLASH_CHECKSUM 205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 208 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 209 210 #define CONFIG_FLASH_CFI_DRIVER 211 #define CONFIG_SYS_FLASH_CFI 212 #define CONFIG_SYS_WRITE_SWAPPED_DATA 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_PROTECTION 215 216 #undef CONFIG_CLOCKS_IN_MHZ 217 218 #define CONFIG_SYS_INIT_RAM_LOCK 1 219 #ifndef CONFIG_SYS_INIT_RAM_LOCK 220 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 221 #else 222 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 223 #endif 224 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 225 226 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 227 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 228 229 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 230 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 231 232 /* Serial Port */ 233 #define CONFIG_SYS_NS16550_SERIAL 234 #define CONFIG_SYS_NS16550_REG_SIZE 1 235 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 236 237 #define CONFIG_SYS_BAUDRATE_TABLE \ 238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 239 240 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 241 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 242 243 /* 244 * I2C 245 */ 246 #define CONFIG_SYS_I2C 247 #define CONFIG_SYS_I2C_FSL 248 #define CONFIG_SYS_FSL_I2C_SPEED 400000 249 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 251 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 252 253 /* 254 * RapidIO MMU 255 */ 256 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 257 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 258 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 259 260 /* 261 * General PCI 262 * Addresses are mapped 1-1. 263 */ 264 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 265 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 266 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 267 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 268 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 269 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 270 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 271 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 272 273 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 274 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 275 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 276 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 277 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 278 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 279 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 280 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 281 282 #if defined(CONFIG_PCI) 283 284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 285 286 #undef CONFIG_EEPRO100 287 #undef CONFIG_TULIP 288 289 #if !defined(CONFIG_PCI_PNP) 290 #define PCI_ENET0_IOADDR 0xe0000000 291 #define PCI_ENET0_MEMADDR 0xe0000000 292 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 293 #endif 294 295 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 296 297 #ifdef CONFIG_SCSI_AHCI 298 #define CONFIG_SATA_ULI5288 299 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 300 #define CONFIG_SYS_SCSI_MAX_LUN 1 301 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 302 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 303 #endif 304 305 #endif /* CONFIG_PCI */ 306 307 #if defined(CONFIG_TSEC_ENET) 308 309 /* #define CONFIG_MII 1 */ /* MII PHY management */ 310 311 #define CONFIG_TSEC1 1 312 #define CONFIG_TSEC1_NAME "eTSEC1" 313 #define CONFIG_TSEC2 1 314 #define CONFIG_TSEC2_NAME "eTSEC2" 315 #define CONFIG_TSEC3 1 316 #define CONFIG_TSEC3_NAME "eTSEC3" 317 #define CONFIG_TSEC4 1 318 #define CONFIG_TSEC4_NAME "eTSEC4" 319 320 #define TSEC1_PHY_ADDR 0x1F 321 #define TSEC2_PHY_ADDR 0x00 322 #define TSEC3_PHY_ADDR 0x01 323 #define TSEC4_PHY_ADDR 0x02 324 #define TSEC1_PHYIDX 0 325 #define TSEC2_PHYIDX 0 326 #define TSEC3_PHYIDX 0 327 #define TSEC4_PHYIDX 0 328 #define TSEC1_FLAGS TSEC_GIGABIT 329 #define TSEC2_FLAGS TSEC_GIGABIT 330 #define TSEC3_FLAGS TSEC_GIGABIT 331 #define TSEC4_FLAGS TSEC_GIGABIT 332 333 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 334 335 #define CONFIG_ETHPRIME "eTSEC1" 336 337 #endif /* CONFIG_TSEC_ENET */ 338 339 /* 340 * BAT0 2G Cacheable, non-guarded 341 * 0x0000_0000 2G DDR 342 */ 343 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 344 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 345 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 346 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 347 348 /* 349 * BAT1 1G Cache-inhibited, guarded 350 * 0x8000_0000 512M PCI-Express 1 Memory 351 * 0xa000_0000 512M PCI-Express 2 Memory 352 * Changed it for operating from 0xd0000000 353 */ 354 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 355 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 356 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 357 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 358 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 359 360 /* 361 * BAT2 512M Cache-inhibited, guarded 362 * 0xc000_0000 512M RapidIO Memory 363 */ 364 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 365 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 366 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 367 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 368 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 369 370 /* 371 * BAT3 4M Cache-inhibited, guarded 372 * 0xf800_0000 4M CCSR 373 */ 374 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 375 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 376 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 377 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 378 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 379 380 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 381 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 382 | BATL_PP_RW | BATL_CACHEINHIBIT \ 383 | BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 385 | BATU_BL_1M | BATU_VS | BATU_VP) 386 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 387 | BATL_PP_RW | BATL_CACHEINHIBIT) 388 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 389 #endif 390 391 /* 392 * BAT4 32M Cache-inhibited, guarded 393 * 0xe200_0000 16M PCI-Express 1 I/O 394 * 0xe300_0000 16M PCI-Express 2 I/0 395 * Note that this is at 0xe0000000 396 */ 397 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 398 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 399 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 400 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 401 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 402 403 /* 404 * BAT5 128K Cacheable, non-guarded 405 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 406 */ 407 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 408 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 409 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 410 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 411 412 /* 413 * BAT6 32M Cache-inhibited, guarded 414 * 0xfe00_0000 32M FLASH 415 */ 416 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 417 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 418 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 419 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 420 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 421 422 /* Map the last 1M of flash where we're running from reset */ 423 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 424 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 425 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 426 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 427 | BATL_MEMCOHERENCE) 428 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 429 430 #define CONFIG_SYS_DBAT7L 0x00000000 431 #define CONFIG_SYS_DBAT7U 0x00000000 432 #define CONFIG_SYS_IBAT7L 0x00000000 433 #define CONFIG_SYS_IBAT7U 0x00000000 434 435 /* 436 * Environment 437 */ 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 439 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 440 #define CONFIG_ENV_SIZE 0x2000 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 #undef CONFIG_WATCHDOG /* watchdog disabled */ 446 447 /* 448 * Miscellaneous configurable options 449 */ 450 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 451 452 /* 453 * For booting Linux, the board info and command line data 454 * have to be in the first 8 MB of memory, since this is 455 * the maximum mapped by the Linux kernel during initialization. 456 */ 457 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 458 459 /* Cache Configuration */ 460 #define CONFIG_SYS_DCACHE_SIZE 32768 461 #define CONFIG_SYS_CACHELINE_SIZE 32 462 #if defined(CONFIG_CMD_KGDB) 463 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 464 #endif 465 466 #if defined(CONFIG_CMD_KGDB) 467 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 468 #endif 469 470 /* 471 * Environment Configuration 472 */ 473 474 #define CONFIG_HAS_ETH0 1 475 #define CONFIG_HAS_ETH1 1 476 #define CONFIG_HAS_ETH2 1 477 #define CONFIG_HAS_ETH3 1 478 479 #define CONFIG_IPADDR 192.168.0.50 480 481 #define CONFIG_HOSTNAME "sbc8641d" 482 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 483 #define CONFIG_BOOTFILE "uImage" 484 485 #define CONFIG_SERVERIP 192.168.0.2 486 #define CONFIG_GATEWAYIP 192.168.0.1 487 #define CONFIG_NETMASK 255.255.255.0 488 489 /* default location for tftp and bootm */ 490 #define CONFIG_LOADADDR 1000000 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "netdev=eth0\0" \ 494 "consoledev=ttyS0\0" \ 495 "ramdiskaddr=2000000\0" \ 496 "ramdiskfile=uRamdisk\0" \ 497 "dtbaddr=400000\0" \ 498 "dtbfile=sbc8641d.dtb\0" \ 499 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 500 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 501 "maxcpus=1" 502 503 #define CONFIG_NFSBOOTCOMMAND \ 504 "setenv bootargs root=/dev/nfs rw " \ 505 "nfsroot=$serverip:$rootpath " \ 506 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 507 "console=$consoledev,$baudrate $othbootargs;" \ 508 "tftp $loadaddr $bootfile;" \ 509 "tftp $dtbaddr $dtbfile;" \ 510 "bootm $loadaddr - $dtbaddr" 511 512 #define CONFIG_RAMBOOTCOMMAND \ 513 "setenv bootargs root=/dev/ram rw " \ 514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $ramdiskaddr $ramdiskfile;" \ 517 "tftp $loadaddr $bootfile;" \ 518 "tftp $dtbaddr $dtbfile;" \ 519 "bootm $loadaddr $ramdiskaddr $dtbaddr" 520 521 #define CONFIG_FLASHBOOTCOMMAND \ 522 "setenv bootargs root=/dev/ram rw " \ 523 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "bootm ffd00000 ffb00000 ffa00000" 526 527 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 528 529 #endif /* __CONFIG_H */ 530