1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * SBC8641D board configuration file 31 * 32 * Make sure you change the MAC address and other network params first, 33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 34 */ 35 36 #ifndef __CONFIG_H 37 #define __CONFIG_H 38 39 /* High Level Configuration Options */ 40 #define CONFIG_MPC86xx 1 /* MPC86xx */ 41 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 43 #define CONFIG_MP 1 /* support multiple processors */ 44 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 45 46 #ifdef RUN_DIAG 47 #define CONFIG_SYS_DIAG_ADDR 0xff800000 48 #endif 49 50 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 51 52 /* 53 * virtual address to be used for temporary mappings. There 54 * should be 128k free at this VA. 55 */ 56 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 57 58 #define CONFIG_PCI 1 /* Enable PCIE */ 59 #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ 60 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ 61 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 62 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 63 64 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 68 69 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 70 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 #define CONFIG_NUM_DDR_CONTROLLERS 2 74 #define CACHE_LINE_INTERLEAVING 0x20000000 75 #define PAGE_INTERLEAVING 0x21000000 76 #define BANK_INTERLEAVING 0x22000000 77 #define SUPER_BANK_INTERLEAVING 0x23000000 78 79 80 #define CONFIG_ALTIVEC 1 81 82 /* 83 * L2CR setup -- make sure this is right for your board! 84 */ 85 #define CONFIG_SYS_L2 86 #define L2_INIT 0 87 #define L2_ENABLE (L2CR_L2E) 88 89 #ifndef CONFIG_SYS_CLK_FREQ 90 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 91 #endif 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 99 /* 100 * Base addresses -- Note these are effective addresses where the 101 * actual resources get mapped (not physical addresses) 102 */ 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 104 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 105 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 106 107 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 108 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 110 111 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 112 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 113 114 /* 115 * DDR Setup 116 */ 117 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 118 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 121 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 122 #define CONFIG_VERY_BIG_RAM 123 124 #define MPC86xx_DDR_SDRAM_CLK_CNTL 125 126 #define CONFIG_NUM_DDR_CONTROLLERS 2 127 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 128 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 129 130 #if defined(CONFIG_SPD_EEPROM) 131 /* 132 * Determine DDR configuration from I2C interface. 133 */ 134 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 135 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 136 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 137 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 138 139 #else 140 /* 141 * Manually set up DDR1 & DDR2 parameters 142 */ 143 144 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 145 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 147 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 148 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 149 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 150 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 151 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 152 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 153 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 154 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 155 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 156 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 157 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 158 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 159 #define CONFIG_SYS_DDR_CFG_2 0x24401000 160 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 161 #define CONFIG_SYS_DDR_MODE_2 0x00000000 162 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 163 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 164 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 165 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 166 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 167 168 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 169 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 170 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 171 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 172 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 173 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 174 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 175 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 176 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 177 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 178 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 179 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 180 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 181 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 182 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 183 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 184 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 185 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 186 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 187 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 188 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 189 190 191 #endif 192 193 /* #define CONFIG_ID_EEPROM 1 194 #define ID_EEPROM_ADDR 0x57 */ 195 196 /* 197 * The SBC8641D contains 16MB flash space at ff000000. 198 */ 199 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 200 201 /* Flash */ 202 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 203 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 204 205 /* 64KB EEPROM */ 206 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 207 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 208 209 /* EPLD - User switches, board id, LEDs */ 210 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 211 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 212 213 /* Local bus SDRAM 128MB */ 214 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 215 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 216 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 217 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 218 219 /* Disk on Chip (DOC) 128MB */ 220 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 221 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 222 223 /* LCD */ 224 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 225 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 226 227 /* Control logic & misc peripherals */ 228 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 229 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 232 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 233 234 #undef CONFIG_SYS_FLASH_CHECKSUM 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 238 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 239 240 #define CONFIG_FLASH_CFI_DRIVER 241 #define CONFIG_SYS_FLASH_CFI 242 #define CONFIG_SYS_WRITE_SWAPPED_DATA 243 #define CONFIG_SYS_FLASH_EMPTY_INFO 244 #define CONFIG_SYS_FLASH_PROTECTION 245 246 #undef CONFIG_CLOCKS_IN_MHZ 247 248 #define CONFIG_SYS_INIT_RAM_LOCK 1 249 #ifndef CONFIG_SYS_INIT_RAM_LOCK 250 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 251 #else 252 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 253 #endif 254 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 255 256 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 257 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 258 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 259 260 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 261 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 262 263 /* Serial Port */ 264 #define CONFIG_CONS_INDEX 1 265 #undef CONFIG_SERIAL_SOFTWARE_FIFO 266 #define CONFIG_SYS_NS16550 267 #define CONFIG_SYS_NS16550_SERIAL 268 #define CONFIG_SYS_NS16550_REG_SIZE 1 269 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 270 271 #define CONFIG_SYS_BAUDRATE_TABLE \ 272 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 273 274 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 275 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 276 277 /* Use the HUSH parser */ 278 #define CONFIG_SYS_HUSH_PARSER 279 #ifdef CONFIG_SYS_HUSH_PARSER 280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 281 #endif 282 283 /* 284 * Pass open firmware flat tree to kernel 285 */ 286 #define CONFIG_OF_LIBFDT 1 287 #define CONFIG_OF_BOARD_SETUP 1 288 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 289 290 #define CONFIG_SYS_64BIT_VSPRINTF 1 291 #define CONFIG_SYS_64BIT_STRTOUL 1 292 293 /* 294 * I2C 295 */ 296 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 297 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 298 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 299 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 300 #define CONFIG_SYS_I2C_SLAVE 0x7F 301 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 302 #define CONFIG_SYS_I2C_OFFSET 0x3100 303 304 /* 305 * RapidIO MMU 306 */ 307 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ 308 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 309 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 316 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 317 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 318 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 319 #define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 320 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS 321 #define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS 322 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 323 324 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 325 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS 326 #define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS 327 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 328 #define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 329 #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS 330 #define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS 331 #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ 332 333 #if defined(CONFIG_PCI) 334 335 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 336 337 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 338 339 #define CONFIG_NET_MULTI 340 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 341 342 #undef CONFIG_EEPRO100 343 #undef CONFIG_TULIP 344 345 #if !defined(CONFIG_PCI_PNP) 346 #define PCI_ENET0_IOADDR 0xe0000000 347 #define PCI_ENET0_MEMADDR 0xe0000000 348 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 349 #endif 350 351 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 352 353 #define CONFIG_DOS_PARTITION 354 #undef CONFIG_SCSI_AHCI 355 356 #ifdef CONFIG_SCSI_AHCI 357 #define CONFIG_SATA_ULI5288 358 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 359 #define CONFIG_SYS_SCSI_MAX_LUN 1 360 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 361 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 362 #endif 363 364 #endif /* CONFIG_PCI */ 365 366 #if defined(CONFIG_TSEC_ENET) 367 368 #ifndef CONFIG_NET_MULTI 369 #define CONFIG_NET_MULTI 1 370 #endif 371 372 /* #define CONFIG_MII 1 */ /* MII PHY management */ 373 374 #define CONFIG_TSEC1 1 375 #define CONFIG_TSEC1_NAME "eTSEC1" 376 #define CONFIG_TSEC2 1 377 #define CONFIG_TSEC2_NAME "eTSEC2" 378 #define CONFIG_TSEC3 1 379 #define CONFIG_TSEC3_NAME "eTSEC3" 380 #define CONFIG_TSEC4 1 381 #define CONFIG_TSEC4_NAME "eTSEC4" 382 383 #define TSEC1_PHY_ADDR 0x1F 384 #define TSEC2_PHY_ADDR 0x00 385 #define TSEC3_PHY_ADDR 0x01 386 #define TSEC4_PHY_ADDR 0x02 387 #define TSEC1_PHYIDX 0 388 #define TSEC2_PHYIDX 0 389 #define TSEC3_PHYIDX 0 390 #define TSEC4_PHYIDX 0 391 #define TSEC1_FLAGS TSEC_GIGABIT 392 #define TSEC2_FLAGS TSEC_GIGABIT 393 #define TSEC3_FLAGS TSEC_GIGABIT 394 #define TSEC4_FLAGS TSEC_GIGABIT 395 396 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 397 398 #define CONFIG_ETHPRIME "eTSEC1" 399 400 #endif /* CONFIG_TSEC_ENET */ 401 402 /* 403 * BAT0 2G Cacheable, non-guarded 404 * 0x0000_0000 2G DDR 405 */ 406 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 407 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 408 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 409 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 410 411 /* 412 * BAT1 1G Cache-inhibited, guarded 413 * 0x8000_0000 512M PCI-Express 1 Memory 414 * 0xa000_0000 512M PCI-Express 2 Memory 415 * Changed it for operating from 0xd0000000 416 */ 417 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 418 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 419 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 421 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 422 423 /* 424 * BAT2 512M Cache-inhibited, guarded 425 * 0xc000_0000 512M RapidIO Memory 426 */ 427 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ 428 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 429 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 430 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 431 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 432 433 /* 434 * BAT3 4M Cache-inhibited, guarded 435 * 0xf800_0000 4M CCSR 436 */ 437 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 438 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 439 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 440 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 441 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 442 443 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 444 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 445 | BATL_PP_RW | BATL_CACHEINHIBIT \ 446 | BATL_GUARDEDSTORAGE) 447 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 448 | BATU_BL_1M | BATU_VS | BATU_VP) 449 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 450 | BATL_PP_RW | BATL_CACHEINHIBIT) 451 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 452 #endif 453 454 /* 455 * BAT4 32M Cache-inhibited, guarded 456 * 0xe200_0000 16M PCI-Express 1 I/O 457 * 0xe300_0000 16M PCI-Express 2 I/0 458 * Note that this is at 0xe0000000 459 */ 460 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ 461 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 462 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 463 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 464 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 465 466 /* 467 * BAT5 128K Cacheable, non-guarded 468 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 469 */ 470 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 471 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 472 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 473 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 474 475 /* 476 * BAT6 32M Cache-inhibited, guarded 477 * 0xfe00_0000 32M FLASH 478 */ 479 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 480 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 481 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 482 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 483 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 484 485 /* Map the last 1M of flash where we're running from reset */ 486 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 487 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 488 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 489 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 490 | BATL_MEMCOHERENCE) 491 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 492 493 #define CONFIG_SYS_DBAT7L 0x00000000 494 #define CONFIG_SYS_DBAT7U 0x00000000 495 #define CONFIG_SYS_IBAT7L 0x00000000 496 #define CONFIG_SYS_IBAT7U 0x00000000 497 498 /* 499 * Environment 500 */ 501 #define CONFIG_ENV_IS_IN_FLASH 1 502 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 503 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 504 #define CONFIG_ENV_SIZE 0x2000 505 506 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 507 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 508 509 #include <config_cmd_default.h> 510 #define CONFIG_CMD_PING 511 #define CONFIG_CMD_I2C 512 #define CONFIG_CMD_REGINFO 513 514 #if defined(CONFIG_PCI) 515 #define CONFIG_CMD_PCI 516 #endif 517 518 #undef CONFIG_WATCHDOG /* watchdog disabled */ 519 520 /* 521 * Miscellaneous configurable options 522 */ 523 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 524 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 525 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 526 527 #if defined(CONFIG_CMD_KGDB) 528 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 529 #else 530 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 531 #endif 532 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 534 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 535 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 536 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 537 538 /* 539 * For booting Linux, the board info and command line data 540 * have to be in the first 8 MB of memory, since this is 541 * the maximum mapped by the Linux kernel during initialization. 542 */ 543 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 544 545 /* Cache Configuration */ 546 #define CONFIG_SYS_DCACHE_SIZE 32768 547 #define CONFIG_SYS_CACHELINE_SIZE 32 548 #if defined(CONFIG_CMD_KGDB) 549 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 550 #endif 551 552 /* 553 * Internal Definitions 554 * 555 * Boot Flags 556 */ 557 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 558 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 559 560 #if defined(CONFIG_CMD_KGDB) 561 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 562 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 563 #endif 564 565 /* 566 * Environment Configuration 567 */ 568 569 /* The mac addresses for all ethernet interface */ 570 #if defined(CONFIG_TSEC_ENET) 571 #define CONFIG_ETHADDR 02:E0:0C:00:00:01 572 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 573 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 574 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 575 #endif 576 577 #define CONFIG_HAS_ETH0 1 578 #define CONFIG_HAS_ETH1 1 579 #define CONFIG_HAS_ETH2 1 580 #define CONFIG_HAS_ETH3 1 581 582 #define CONFIG_IPADDR 192.168.0.50 583 584 #define CONFIG_HOSTNAME sbc8641d 585 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx 586 #define CONFIG_BOOTFILE uImage 587 588 #define CONFIG_SERVERIP 192.168.0.2 589 #define CONFIG_GATEWAYIP 192.168.0.1 590 #define CONFIG_NETMASK 255.255.255.0 591 592 /* default location for tftp and bootm */ 593 #define CONFIG_LOADADDR 1000000 594 595 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 596 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 597 598 #define CONFIG_BAUDRATE 115200 599 600 #define CONFIG_EXTRA_ENV_SETTINGS \ 601 "netdev=eth0\0" \ 602 "consoledev=ttyS0\0" \ 603 "ramdiskaddr=2000000\0" \ 604 "ramdiskfile=uRamdisk\0" \ 605 "dtbaddr=400000\0" \ 606 "dtbfile=sbc8641d.dtb\0" \ 607 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 608 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 609 "maxcpus=1" 610 611 #define CONFIG_NFSBOOTCOMMAND \ 612 "setenv bootargs root=/dev/nfs rw " \ 613 "nfsroot=$serverip:$rootpath " \ 614 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 615 "console=$consoledev,$baudrate $othbootargs;" \ 616 "tftp $loadaddr $bootfile;" \ 617 "tftp $dtbaddr $dtbfile;" \ 618 "bootm $loadaddr - $dtbaddr" 619 620 #define CONFIG_RAMBOOTCOMMAND \ 621 "setenv bootargs root=/dev/ram rw " \ 622 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "tftp $ramdiskaddr $ramdiskfile;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $dtbaddr $dtbfile;" \ 627 "bootm $loadaddr $ramdiskaddr $dtbaddr" 628 629 #define CONFIG_FLASHBOOTCOMMAND \ 630 "setenv bootargs root=/dev/ram rw " \ 631 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "bootm ffd00000 ffb00000 ffa00000" 634 635 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 636 637 #endif /* __CONFIG_H */ 638