1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MP 1 /* support multiple processors */ 25 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 26 27 #ifdef RUN_DIAG 28 #define CONFIG_SYS_DIAG_ADDR 0xff800000 29 #endif 30 31 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 32 33 /* 34 * virtual address to be used for temporary mappings. There 35 * should be 128k free at this VA. 36 */ 37 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 38 39 #define CONFIG_SYS_SRIO 40 #define CONFIG_SRIO1 /* SRIO port 1 */ 41 42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 50 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 51 52 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 53 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 56 #define CACHE_LINE_INTERLEAVING 0x20000000 57 #define PAGE_INTERLEAVING 0x21000000 58 #define BANK_INTERLEAVING 0x22000000 59 #define SUPER_BANK_INTERLEAVING 0x23000000 60 61 #define CONFIG_ALTIVEC 1 62 63 /* 64 * L2CR setup -- make sure this is right for your board! 65 */ 66 #define CONFIG_SYS_L2 67 #define L2_INIT 0 68 #define L2_ENABLE (L2CR_L2E) 69 70 #ifndef CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 72 #endif 73 74 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 76 #define CONFIG_SYS_MEMTEST_END 0x00400000 77 78 /* 79 * Base addresses -- Note these are effective addresses where the 80 * actual resources get mapped (not physical addresses) 81 */ 82 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 83 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 84 85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 86 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 88 89 /* 90 * DDR Setup 91 */ 92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 93 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 96 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 97 #define CONFIG_VERY_BIG_RAM 98 99 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 100 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 101 102 #if defined(CONFIG_SPD_EEPROM) 103 /* 104 * Determine DDR configuration from I2C interface. 105 */ 106 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 107 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 108 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 109 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 110 111 #else 112 /* 113 * Manually set up DDR1 & DDR2 parameters 114 */ 115 116 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 117 118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 119 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 120 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 121 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 123 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 124 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 125 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 126 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 127 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 128 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 129 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 130 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 131 #define CONFIG_SYS_DDR_CFG_2 0x24401000 132 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 133 #define CONFIG_SYS_DDR_MODE_2 0x00000000 134 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 135 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 136 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 137 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 138 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 139 140 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 141 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 142 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 143 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 144 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 145 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 146 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 147 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 148 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 149 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 150 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 151 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 152 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 153 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 154 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 155 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 156 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 157 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 158 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 159 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 160 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 161 162 #endif 163 164 /* #define CONFIG_ID_EEPROM 1 165 #define ID_EEPROM_ADDR 0x57 */ 166 167 /* 168 * The SBC8641D contains 16MB flash space at ff000000. 169 */ 170 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 171 172 /* Flash */ 173 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 174 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 175 176 /* 64KB EEPROM */ 177 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 178 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 179 180 /* EPLD - User switches, board id, LEDs */ 181 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 182 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 183 184 /* Local bus SDRAM 128MB */ 185 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 186 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 187 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 188 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 189 190 /* Disk on Chip (DOC) 128MB */ 191 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 192 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 193 194 /* LCD */ 195 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 196 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 197 198 /* Control logic & misc peripherals */ 199 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 200 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 204 205 #undef CONFIG_SYS_FLASH_CHECKSUM 206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 209 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 210 211 #define CONFIG_FLASH_CFI_DRIVER 212 #define CONFIG_SYS_FLASH_CFI 213 #define CONFIG_SYS_WRITE_SWAPPED_DATA 214 #define CONFIG_SYS_FLASH_EMPTY_INFO 215 #define CONFIG_SYS_FLASH_PROTECTION 216 217 #undef CONFIG_CLOCKS_IN_MHZ 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #ifndef CONFIG_SYS_INIT_RAM_LOCK 221 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 222 #else 223 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 224 #endif 225 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 226 227 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 229 230 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 231 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 232 233 /* Serial Port */ 234 #define CONFIG_SYS_NS16550_SERIAL 235 #define CONFIG_SYS_NS16550_REG_SIZE 1 236 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 237 238 #define CONFIG_SYS_BAUDRATE_TABLE \ 239 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 240 241 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 242 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 243 244 /* 245 * I2C 246 */ 247 #define CONFIG_SYS_I2C 248 #define CONFIG_SYS_I2C_FSL 249 #define CONFIG_SYS_FSL_I2C_SPEED 400000 250 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 251 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 252 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 253 254 /* 255 * RapidIO MMU 256 */ 257 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 258 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 259 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 260 261 /* 262 * General PCI 263 * Addresses are mapped 1-1. 264 */ 265 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 266 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 267 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 268 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 269 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 270 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 271 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 272 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 273 274 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 275 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 276 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 277 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 278 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 279 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 280 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 281 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 282 283 #if defined(CONFIG_PCI) 284 285 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 286 287 #undef CONFIG_EEPRO100 288 #undef CONFIG_TULIP 289 290 #if !defined(CONFIG_PCI_PNP) 291 #define PCI_ENET0_IOADDR 0xe0000000 292 #define PCI_ENET0_MEMADDR 0xe0000000 293 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 294 #endif 295 296 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 297 298 #ifdef CONFIG_SCSI_AHCI 299 #define CONFIG_SATA_ULI5288 300 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 301 #define CONFIG_SYS_SCSI_MAX_LUN 1 302 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 303 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 304 #endif 305 306 #endif /* CONFIG_PCI */ 307 308 #if defined(CONFIG_TSEC_ENET) 309 310 /* #define CONFIG_MII 1 */ /* MII PHY management */ 311 312 #define CONFIG_TSEC1 1 313 #define CONFIG_TSEC1_NAME "eTSEC1" 314 #define CONFIG_TSEC2 1 315 #define CONFIG_TSEC2_NAME "eTSEC2" 316 #define CONFIG_TSEC3 1 317 #define CONFIG_TSEC3_NAME "eTSEC3" 318 #define CONFIG_TSEC4 1 319 #define CONFIG_TSEC4_NAME "eTSEC4" 320 321 #define TSEC1_PHY_ADDR 0x1F 322 #define TSEC2_PHY_ADDR 0x00 323 #define TSEC3_PHY_ADDR 0x01 324 #define TSEC4_PHY_ADDR 0x02 325 #define TSEC1_PHYIDX 0 326 #define TSEC2_PHYIDX 0 327 #define TSEC3_PHYIDX 0 328 #define TSEC4_PHYIDX 0 329 #define TSEC1_FLAGS TSEC_GIGABIT 330 #define TSEC2_FLAGS TSEC_GIGABIT 331 #define TSEC3_FLAGS TSEC_GIGABIT 332 #define TSEC4_FLAGS TSEC_GIGABIT 333 334 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 335 336 #define CONFIG_ETHPRIME "eTSEC1" 337 338 #endif /* CONFIG_TSEC_ENET */ 339 340 /* 341 * BAT0 2G Cacheable, non-guarded 342 * 0x0000_0000 2G DDR 343 */ 344 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 345 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 346 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 347 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 348 349 /* 350 * BAT1 1G Cache-inhibited, guarded 351 * 0x8000_0000 512M PCI-Express 1 Memory 352 * 0xa000_0000 512M PCI-Express 2 Memory 353 * Changed it for operating from 0xd0000000 354 */ 355 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 356 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 357 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 358 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 359 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 360 361 /* 362 * BAT2 512M Cache-inhibited, guarded 363 * 0xc000_0000 512M RapidIO Memory 364 */ 365 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 366 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 368 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 369 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 370 371 /* 372 * BAT3 4M Cache-inhibited, guarded 373 * 0xf800_0000 4M CCSR 374 */ 375 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 376 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 377 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 379 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 380 381 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 382 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 383 | BATL_PP_RW | BATL_CACHEINHIBIT \ 384 | BATL_GUARDEDSTORAGE) 385 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 386 | BATU_BL_1M | BATU_VS | BATU_VP) 387 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 388 | BATL_PP_RW | BATL_CACHEINHIBIT) 389 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 390 #endif 391 392 /* 393 * BAT4 32M Cache-inhibited, guarded 394 * 0xe200_0000 16M PCI-Express 1 I/O 395 * 0xe300_0000 16M PCI-Express 2 I/0 396 * Note that this is at 0xe0000000 397 */ 398 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 399 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 400 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 401 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 402 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 403 404 /* 405 * BAT5 128K Cacheable, non-guarded 406 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 407 */ 408 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 409 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 410 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 411 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 412 413 /* 414 * BAT6 32M Cache-inhibited, guarded 415 * 0xfe00_0000 32M FLASH 416 */ 417 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 418 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 419 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 421 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 422 423 /* Map the last 1M of flash where we're running from reset */ 424 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 425 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 426 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 427 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 428 | BATL_MEMCOHERENCE) 429 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 430 431 #define CONFIG_SYS_DBAT7L 0x00000000 432 #define CONFIG_SYS_DBAT7U 0x00000000 433 #define CONFIG_SYS_IBAT7L 0x00000000 434 #define CONFIG_SYS_IBAT7U 0x00000000 435 436 /* 437 * Environment 438 */ 439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 440 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 441 #define CONFIG_ENV_SIZE 0x2000 442 443 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 444 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 445 446 #undef CONFIG_WATCHDOG /* watchdog disabled */ 447 448 /* 449 * Miscellaneous configurable options 450 */ 451 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 452 453 /* 454 * For booting Linux, the board info and command line data 455 * have to be in the first 8 MB of memory, since this is 456 * the maximum mapped by the Linux kernel during initialization. 457 */ 458 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 459 460 /* Cache Configuration */ 461 #define CONFIG_SYS_DCACHE_SIZE 32768 462 #define CONFIG_SYS_CACHELINE_SIZE 32 463 #if defined(CONFIG_CMD_KGDB) 464 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 465 #endif 466 467 #if defined(CONFIG_CMD_KGDB) 468 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 469 #endif 470 471 /* 472 * Environment Configuration 473 */ 474 475 #define CONFIG_HAS_ETH0 1 476 #define CONFIG_HAS_ETH1 1 477 #define CONFIG_HAS_ETH2 1 478 #define CONFIG_HAS_ETH3 1 479 480 #define CONFIG_IPADDR 192.168.0.50 481 482 #define CONFIG_HOSTNAME "sbc8641d" 483 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 484 #define CONFIG_BOOTFILE "uImage" 485 486 #define CONFIG_SERVERIP 192.168.0.2 487 #define CONFIG_GATEWAYIP 192.168.0.1 488 #define CONFIG_NETMASK 255.255.255.0 489 490 /* default location for tftp and bootm */ 491 #define CONFIG_LOADADDR 1000000 492 493 #define CONFIG_EXTRA_ENV_SETTINGS \ 494 "netdev=eth0\0" \ 495 "consoledev=ttyS0\0" \ 496 "ramdiskaddr=2000000\0" \ 497 "ramdiskfile=uRamdisk\0" \ 498 "dtbaddr=400000\0" \ 499 "dtbfile=sbc8641d.dtb\0" \ 500 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 501 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 502 "maxcpus=1" 503 504 #define CONFIG_NFSBOOTCOMMAND \ 505 "setenv bootargs root=/dev/nfs rw " \ 506 "nfsroot=$serverip:$rootpath " \ 507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 508 "console=$consoledev,$baudrate $othbootargs;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "tftp $dtbaddr $dtbfile;" \ 511 "bootm $loadaddr - $dtbaddr" 512 513 #define CONFIG_RAMBOOTCOMMAND \ 514 "setenv bootargs root=/dev/ram rw " \ 515 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 516 "console=$consoledev,$baudrate $othbootargs;" \ 517 "tftp $ramdiskaddr $ramdiskfile;" \ 518 "tftp $loadaddr $bootfile;" \ 519 "tftp $dtbaddr $dtbfile;" \ 520 "bootm $loadaddr $ramdiskaddr $dtbaddr" 521 522 #define CONFIG_FLASHBOOTCOMMAND \ 523 "setenv bootargs root=/dev/ram rw " \ 524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "bootm ffd00000 ffb00000 ffa00000" 527 528 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 529 530 #endif /* __CONFIG_H */ 531