1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 #define CONFIG_SYS_GENERIC_BOARD 24 25 /* High Level Configuration Options */ 26 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 27 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 28 #define CONFIG_MP 1 /* support multiple processors */ 29 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 30 31 #define CONFIG_SYS_TEXT_BASE 0xfff00000 32 33 #ifdef RUN_DIAG 34 #define CONFIG_SYS_DIAG_ADDR 0xff800000 35 #endif 36 37 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 38 39 /* 40 * virtual address to be used for temporary mappings. There 41 * should be 128k free at this VA. 42 */ 43 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 44 45 #define CONFIG_SYS_SRIO 46 #define CONFIG_SRIO1 /* SRIO port 1 */ 47 48 #define CONFIG_PCI 1 /* Enable PCIE */ 49 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 50 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 59 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 60 61 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 62 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 63 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 64 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 65 #define CONFIG_NUM_DDR_CONTROLLERS 2 66 #define CACHE_LINE_INTERLEAVING 0x20000000 67 #define PAGE_INTERLEAVING 0x21000000 68 #define BANK_INTERLEAVING 0x22000000 69 #define SUPER_BANK_INTERLEAVING 0x23000000 70 71 72 #define CONFIG_ALTIVEC 1 73 74 /* 75 * L2CR setup -- make sure this is right for your board! 76 */ 77 #define CONFIG_SYS_L2 78 #define L2_INIT 0 79 #define L2_ENABLE (L2CR_L2E) 80 81 #ifndef CONFIG_SYS_CLK_FREQ 82 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 83 #endif 84 85 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 86 87 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 88 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 89 #define CONFIG_SYS_MEMTEST_END 0x00400000 90 91 /* 92 * Base addresses -- Note these are effective addresses where the 93 * actual resources get mapped (not physical addresses) 94 */ 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 96 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 98 99 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 100 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 101 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 102 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 107 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 110 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 111 #define CONFIG_VERY_BIG_RAM 112 113 #define CONFIG_NUM_DDR_CONTROLLERS 2 114 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 115 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 116 117 #if defined(CONFIG_SPD_EEPROM) 118 /* 119 * Determine DDR configuration from I2C interface. 120 */ 121 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 122 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 123 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 124 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 125 126 #else 127 /* 128 * Manually set up DDR1 & DDR2 parameters 129 */ 130 131 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 132 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 134 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 135 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 136 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 137 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 138 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 139 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 140 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 142 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 143 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 144 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 145 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 146 #define CONFIG_SYS_DDR_CFG_2 0x24401000 147 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 148 #define CONFIG_SYS_DDR_MODE_2 0x00000000 149 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 150 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 151 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 152 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 153 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 154 155 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 156 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 157 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 158 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 159 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 160 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 161 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 162 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 163 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 164 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 165 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 166 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 167 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 168 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 169 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 170 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 171 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 172 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 173 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 174 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 175 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 176 177 178 #endif 179 180 /* #define CONFIG_ID_EEPROM 1 181 #define ID_EEPROM_ADDR 0x57 */ 182 183 /* 184 * The SBC8641D contains 16MB flash space at ff000000. 185 */ 186 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 187 188 /* Flash */ 189 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 190 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 191 192 /* 64KB EEPROM */ 193 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 194 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 195 196 /* EPLD - User switches, board id, LEDs */ 197 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 198 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 199 200 /* Local bus SDRAM 128MB */ 201 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 202 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 203 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 204 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 205 206 /* Disk on Chip (DOC) 128MB */ 207 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 208 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 209 210 /* LCD */ 211 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 212 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 213 214 /* Control logic & misc peripherals */ 215 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 216 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 220 221 #undef CONFIG_SYS_FLASH_CHECKSUM 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 225 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 226 227 #define CONFIG_FLASH_CFI_DRIVER 228 #define CONFIG_SYS_FLASH_CFI 229 #define CONFIG_SYS_WRITE_SWAPPED_DATA 230 #define CONFIG_SYS_FLASH_EMPTY_INFO 231 #define CONFIG_SYS_FLASH_PROTECTION 232 233 #undef CONFIG_CLOCKS_IN_MHZ 234 235 #define CONFIG_SYS_INIT_RAM_LOCK 1 236 #ifndef CONFIG_SYS_INIT_RAM_LOCK 237 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 238 #else 239 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 240 #endif 241 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 242 243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 244 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 245 246 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 247 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 248 249 /* Serial Port */ 250 #define CONFIG_CONS_INDEX 1 251 #define CONFIG_SYS_NS16550 252 #define CONFIG_SYS_NS16550_SERIAL 253 #define CONFIG_SYS_NS16550_REG_SIZE 1 254 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 255 256 #define CONFIG_SYS_BAUDRATE_TABLE \ 257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 258 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 261 262 /* Use the HUSH parser */ 263 #define CONFIG_SYS_HUSH_PARSER 264 #ifdef CONFIG_SYS_HUSH_PARSER 265 #endif 266 267 /* 268 * Pass open firmware flat tree to kernel 269 */ 270 #define CONFIG_OF_LIBFDT 1 271 #define CONFIG_OF_BOARD_SETUP 1 272 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 273 274 /* 275 * I2C 276 */ 277 #define CONFIG_SYS_I2C 278 #define CONFIG_SYS_I2C_FSL 279 #define CONFIG_SYS_FSL_I2C_SPEED 400000 280 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 281 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 282 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 283 284 /* 285 * RapidIO MMU 286 */ 287 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 288 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 289 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 290 291 /* 292 * General PCI 293 * Addresses are mapped 1-1. 294 */ 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 297 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 298 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 299 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 300 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 301 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 302 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 303 304 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 305 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 306 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 307 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 308 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 309 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 310 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 311 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 312 313 #if defined(CONFIG_PCI) 314 315 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 316 317 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 318 319 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 320 321 #undef CONFIG_EEPRO100 322 #undef CONFIG_TULIP 323 324 #if !defined(CONFIG_PCI_PNP) 325 #define PCI_ENET0_IOADDR 0xe0000000 326 #define PCI_ENET0_MEMADDR 0xe0000000 327 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 328 #endif 329 330 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 331 332 #define CONFIG_DOS_PARTITION 333 #undef CONFIG_SCSI_AHCI 334 335 #ifdef CONFIG_SCSI_AHCI 336 #define CONFIG_SATA_ULI5288 337 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 338 #define CONFIG_SYS_SCSI_MAX_LUN 1 339 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 340 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 341 #endif 342 343 #endif /* CONFIG_PCI */ 344 345 #if defined(CONFIG_TSEC_ENET) 346 347 /* #define CONFIG_MII 1 */ /* MII PHY management */ 348 349 #define CONFIG_TSEC1 1 350 #define CONFIG_TSEC1_NAME "eTSEC1" 351 #define CONFIG_TSEC2 1 352 #define CONFIG_TSEC2_NAME "eTSEC2" 353 #define CONFIG_TSEC3 1 354 #define CONFIG_TSEC3_NAME "eTSEC3" 355 #define CONFIG_TSEC4 1 356 #define CONFIG_TSEC4_NAME "eTSEC4" 357 358 #define TSEC1_PHY_ADDR 0x1F 359 #define TSEC2_PHY_ADDR 0x00 360 #define TSEC3_PHY_ADDR 0x01 361 #define TSEC4_PHY_ADDR 0x02 362 #define TSEC1_PHYIDX 0 363 #define TSEC2_PHYIDX 0 364 #define TSEC3_PHYIDX 0 365 #define TSEC4_PHYIDX 0 366 #define TSEC1_FLAGS TSEC_GIGABIT 367 #define TSEC2_FLAGS TSEC_GIGABIT 368 #define TSEC3_FLAGS TSEC_GIGABIT 369 #define TSEC4_FLAGS TSEC_GIGABIT 370 371 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 372 373 #define CONFIG_ETHPRIME "eTSEC1" 374 375 #endif /* CONFIG_TSEC_ENET */ 376 377 /* 378 * BAT0 2G Cacheable, non-guarded 379 * 0x0000_0000 2G DDR 380 */ 381 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 382 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 383 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 384 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 385 386 /* 387 * BAT1 1G Cache-inhibited, guarded 388 * 0x8000_0000 512M PCI-Express 1 Memory 389 * 0xa000_0000 512M PCI-Express 2 Memory 390 * Changed it for operating from 0xd0000000 391 */ 392 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 393 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 394 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 395 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 396 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 397 398 /* 399 * BAT2 512M Cache-inhibited, guarded 400 * 0xc000_0000 512M RapidIO Memory 401 */ 402 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 403 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 404 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 405 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 406 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 407 408 /* 409 * BAT3 4M Cache-inhibited, guarded 410 * 0xf800_0000 4M CCSR 411 */ 412 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 413 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 414 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 415 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 416 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 417 418 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 419 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 420 | BATL_PP_RW | BATL_CACHEINHIBIT \ 421 | BATL_GUARDEDSTORAGE) 422 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 423 | BATU_BL_1M | BATU_VS | BATU_VP) 424 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 425 | BATL_PP_RW | BATL_CACHEINHIBIT) 426 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 427 #endif 428 429 /* 430 * BAT4 32M Cache-inhibited, guarded 431 * 0xe200_0000 16M PCI-Express 1 I/O 432 * 0xe300_0000 16M PCI-Express 2 I/0 433 * Note that this is at 0xe0000000 434 */ 435 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 436 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 438 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 439 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 440 441 /* 442 * BAT5 128K Cacheable, non-guarded 443 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 444 */ 445 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 446 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 447 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 448 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 449 450 /* 451 * BAT6 32M Cache-inhibited, guarded 452 * 0xfe00_0000 32M FLASH 453 */ 454 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 455 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 456 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 457 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 458 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 459 460 /* Map the last 1M of flash where we're running from reset */ 461 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 462 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 463 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 464 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 465 | BATL_MEMCOHERENCE) 466 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 467 468 #define CONFIG_SYS_DBAT7L 0x00000000 469 #define CONFIG_SYS_DBAT7U 0x00000000 470 #define CONFIG_SYS_IBAT7L 0x00000000 471 #define CONFIG_SYS_IBAT7U 0x00000000 472 473 /* 474 * Environment 475 */ 476 #define CONFIG_ENV_IS_IN_FLASH 1 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 478 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 479 #define CONFIG_ENV_SIZE 0x2000 480 481 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 482 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 483 484 #define CONFIG_CMD_PING 485 #define CONFIG_CMD_I2C 486 #define CONFIG_CMD_REGINFO 487 488 #if defined(CONFIG_PCI) 489 #define CONFIG_CMD_PCI 490 #endif 491 492 #undef CONFIG_WATCHDOG /* watchdog disabled */ 493 494 /* 495 * Miscellaneous configurable options 496 */ 497 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 498 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 499 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 500 501 #if defined(CONFIG_CMD_KGDB) 502 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 503 #else 504 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 505 #endif 506 507 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 508 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 509 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 510 511 /* 512 * For booting Linux, the board info and command line data 513 * have to be in the first 8 MB of memory, since this is 514 * the maximum mapped by the Linux kernel during initialization. 515 */ 516 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 517 518 /* Cache Configuration */ 519 #define CONFIG_SYS_DCACHE_SIZE 32768 520 #define CONFIG_SYS_CACHELINE_SIZE 32 521 #if defined(CONFIG_CMD_KGDB) 522 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 523 #endif 524 525 #if defined(CONFIG_CMD_KGDB) 526 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 527 #endif 528 529 /* 530 * Environment Configuration 531 */ 532 533 #define CONFIG_HAS_ETH0 1 534 #define CONFIG_HAS_ETH1 1 535 #define CONFIG_HAS_ETH2 1 536 #define CONFIG_HAS_ETH3 1 537 538 #define CONFIG_IPADDR 192.168.0.50 539 540 #define CONFIG_HOSTNAME sbc8641d 541 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 542 #define CONFIG_BOOTFILE "uImage" 543 544 #define CONFIG_SERVERIP 192.168.0.2 545 #define CONFIG_GATEWAYIP 192.168.0.1 546 #define CONFIG_NETMASK 255.255.255.0 547 548 /* default location for tftp and bootm */ 549 #define CONFIG_LOADADDR 1000000 550 551 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 552 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 553 554 #define CONFIG_BAUDRATE 115200 555 556 #define CONFIG_EXTRA_ENV_SETTINGS \ 557 "netdev=eth0\0" \ 558 "consoledev=ttyS0\0" \ 559 "ramdiskaddr=2000000\0" \ 560 "ramdiskfile=uRamdisk\0" \ 561 "dtbaddr=400000\0" \ 562 "dtbfile=sbc8641d.dtb\0" \ 563 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 564 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 565 "maxcpus=1" 566 567 #define CONFIG_NFSBOOTCOMMAND \ 568 "setenv bootargs root=/dev/nfs rw " \ 569 "nfsroot=$serverip:$rootpath " \ 570 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 571 "console=$consoledev,$baudrate $othbootargs;" \ 572 "tftp $loadaddr $bootfile;" \ 573 "tftp $dtbaddr $dtbfile;" \ 574 "bootm $loadaddr - $dtbaddr" 575 576 #define CONFIG_RAMBOOTCOMMAND \ 577 "setenv bootargs root=/dev/ram rw " \ 578 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 579 "console=$consoledev,$baudrate $othbootargs;" \ 580 "tftp $ramdiskaddr $ramdiskfile;" \ 581 "tftp $loadaddr $bootfile;" \ 582 "tftp $dtbaddr $dtbfile;" \ 583 "bootm $loadaddr $ramdiskaddr $dtbaddr" 584 585 #define CONFIG_FLASHBOOTCOMMAND \ 586 "setenv bootargs root=/dev/ram rw " \ 587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 588 "console=$consoledev,$baudrate $othbootargs;" \ 589 "bootm ffd00000 ffb00000 ffa00000" 590 591 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 592 593 #endif /* __CONFIG_H */ 594