1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MPC86xx 1 /* MPC86xx */ 25 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 26 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 27 #define CONFIG_MP 1 /* support multiple processors */ 28 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 29 30 #define CONFIG_SYS_TEXT_BASE 0xfff00000 31 32 #ifdef RUN_DIAG 33 #define CONFIG_SYS_DIAG_ADDR 0xff800000 34 #endif 35 36 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 37 38 /* 39 * virtual address to be used for temporary mappings. There 40 * should be 128k free at this VA. 41 */ 42 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 43 44 #define CONFIG_SYS_SRIO 45 #define CONFIG_SRIO1 /* SRIO port 1 */ 46 47 #define CONFIG_PCI 1 /* Enable PCIE */ 48 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 49 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 58 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 59 60 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 61 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 63 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 64 #define CONFIG_NUM_DDR_CONTROLLERS 2 65 #define CACHE_LINE_INTERLEAVING 0x20000000 66 #define PAGE_INTERLEAVING 0x21000000 67 #define BANK_INTERLEAVING 0x22000000 68 #define SUPER_BANK_INTERLEAVING 0x23000000 69 70 71 #define CONFIG_ALTIVEC 1 72 73 /* 74 * L2CR setup -- make sure this is right for your board! 75 */ 76 #define CONFIG_SYS_L2 77 #define L2_INIT 0 78 #define L2_ENABLE (L2CR_L2E) 79 80 #ifndef CONFIG_SYS_CLK_FREQ 81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 82 #endif 83 84 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 85 86 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 87 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 88 #define CONFIG_SYS_MEMTEST_END 0x00400000 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 95 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 96 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 97 98 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 99 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 100 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 101 102 /* 103 * DDR Setup 104 */ 105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 106 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 108 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 109 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 110 #define CONFIG_VERY_BIG_RAM 111 112 #define CONFIG_NUM_DDR_CONTROLLERS 2 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 114 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 115 116 #if defined(CONFIG_SPD_EEPROM) 117 /* 118 * Determine DDR configuration from I2C interface. 119 */ 120 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 121 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 122 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 123 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 124 125 #else 126 /* 127 * Manually set up DDR1 & DDR2 parameters 128 */ 129 130 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 131 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 133 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 134 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 135 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 136 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 137 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 138 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 139 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 141 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 142 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 143 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 144 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 145 #define CONFIG_SYS_DDR_CFG_2 0x24401000 146 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 147 #define CONFIG_SYS_DDR_MODE_2 0x00000000 148 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 149 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 150 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 151 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 152 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 153 154 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 155 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 156 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 157 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 158 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 159 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 160 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 161 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 162 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 163 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 164 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 165 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 166 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 167 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 168 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 169 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 170 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 171 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 172 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 173 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 174 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 175 176 177 #endif 178 179 /* #define CONFIG_ID_EEPROM 1 180 #define ID_EEPROM_ADDR 0x57 */ 181 182 /* 183 * The SBC8641D contains 16MB flash space at ff000000. 184 */ 185 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 186 187 /* Flash */ 188 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 189 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 190 191 /* 64KB EEPROM */ 192 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 193 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 194 195 /* EPLD - User switches, board id, LEDs */ 196 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 197 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 198 199 /* Local bus SDRAM 128MB */ 200 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 201 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 202 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 203 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 204 205 /* Disk on Chip (DOC) 128MB */ 206 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 207 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 208 209 /* LCD */ 210 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 211 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 212 213 /* Control logic & misc peripherals */ 214 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 215 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 216 217 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 218 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 219 220 #undef CONFIG_SYS_FLASH_CHECKSUM 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 224 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 225 226 #define CONFIG_FLASH_CFI_DRIVER 227 #define CONFIG_SYS_FLASH_CFI 228 #define CONFIG_SYS_WRITE_SWAPPED_DATA 229 #define CONFIG_SYS_FLASH_EMPTY_INFO 230 #define CONFIG_SYS_FLASH_PROTECTION 231 232 #undef CONFIG_CLOCKS_IN_MHZ 233 234 #define CONFIG_SYS_INIT_RAM_LOCK 1 235 #ifndef CONFIG_SYS_INIT_RAM_LOCK 236 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 237 #else 238 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 239 #endif 240 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 241 242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 244 245 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 246 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 247 248 /* Serial Port */ 249 #define CONFIG_CONS_INDEX 1 250 #define CONFIG_SYS_NS16550 251 #define CONFIG_SYS_NS16550_SERIAL 252 #define CONFIG_SYS_NS16550_REG_SIZE 1 253 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 254 255 #define CONFIG_SYS_BAUDRATE_TABLE \ 256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 257 258 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 259 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 260 261 /* Use the HUSH parser */ 262 #define CONFIG_SYS_HUSH_PARSER 263 #ifdef CONFIG_SYS_HUSH_PARSER 264 #endif 265 266 /* 267 * Pass open firmware flat tree to kernel 268 */ 269 #define CONFIG_OF_LIBFDT 1 270 #define CONFIG_OF_BOARD_SETUP 1 271 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 272 273 /* 274 * I2C 275 */ 276 #define CONFIG_SYS_I2C 277 #define CONFIG_SYS_I2C_FSL 278 #define CONFIG_SYS_FSL_I2C_SPEED 400000 279 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 280 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 281 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 282 283 /* 284 * RapidIO MMU 285 */ 286 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 287 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 288 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 289 290 /* 291 * General PCI 292 * Addresses are mapped 1-1. 293 */ 294 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 295 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 296 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 299 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 300 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 301 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 302 303 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 304 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 305 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 306 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 307 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 308 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 309 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 310 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 311 312 #if defined(CONFIG_PCI) 313 314 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 315 316 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 317 318 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 319 320 #undef CONFIG_EEPRO100 321 #undef CONFIG_TULIP 322 323 #if !defined(CONFIG_PCI_PNP) 324 #define PCI_ENET0_IOADDR 0xe0000000 325 #define PCI_ENET0_MEMADDR 0xe0000000 326 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 327 #endif 328 329 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 330 331 #define CONFIG_DOS_PARTITION 332 #undef CONFIG_SCSI_AHCI 333 334 #ifdef CONFIG_SCSI_AHCI 335 #define CONFIG_SATA_ULI5288 336 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 337 #define CONFIG_SYS_SCSI_MAX_LUN 1 338 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 339 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 340 #endif 341 342 #endif /* CONFIG_PCI */ 343 344 #if defined(CONFIG_TSEC_ENET) 345 346 /* #define CONFIG_MII 1 */ /* MII PHY management */ 347 348 #define CONFIG_TSEC1 1 349 #define CONFIG_TSEC1_NAME "eTSEC1" 350 #define CONFIG_TSEC2 1 351 #define CONFIG_TSEC2_NAME "eTSEC2" 352 #define CONFIG_TSEC3 1 353 #define CONFIG_TSEC3_NAME "eTSEC3" 354 #define CONFIG_TSEC4 1 355 #define CONFIG_TSEC4_NAME "eTSEC4" 356 357 #define TSEC1_PHY_ADDR 0x1F 358 #define TSEC2_PHY_ADDR 0x00 359 #define TSEC3_PHY_ADDR 0x01 360 #define TSEC4_PHY_ADDR 0x02 361 #define TSEC1_PHYIDX 0 362 #define TSEC2_PHYIDX 0 363 #define TSEC3_PHYIDX 0 364 #define TSEC4_PHYIDX 0 365 #define TSEC1_FLAGS TSEC_GIGABIT 366 #define TSEC2_FLAGS TSEC_GIGABIT 367 #define TSEC3_FLAGS TSEC_GIGABIT 368 #define TSEC4_FLAGS TSEC_GIGABIT 369 370 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 371 372 #define CONFIG_ETHPRIME "eTSEC1" 373 374 #endif /* CONFIG_TSEC_ENET */ 375 376 /* 377 * BAT0 2G Cacheable, non-guarded 378 * 0x0000_0000 2G DDR 379 */ 380 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 381 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 382 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 383 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 384 385 /* 386 * BAT1 1G Cache-inhibited, guarded 387 * 0x8000_0000 512M PCI-Express 1 Memory 388 * 0xa000_0000 512M PCI-Express 2 Memory 389 * Changed it for operating from 0xd0000000 390 */ 391 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 392 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 393 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 394 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 395 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 396 397 /* 398 * BAT2 512M Cache-inhibited, guarded 399 * 0xc000_0000 512M RapidIO Memory 400 */ 401 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 402 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 403 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 404 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 405 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 406 407 /* 408 * BAT3 4M Cache-inhibited, guarded 409 * 0xf800_0000 4M CCSR 410 */ 411 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 412 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 413 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 414 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 415 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 416 417 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 418 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 419 | BATL_PP_RW | BATL_CACHEINHIBIT \ 420 | BATL_GUARDEDSTORAGE) 421 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 422 | BATU_BL_1M | BATU_VS | BATU_VP) 423 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 424 | BATL_PP_RW | BATL_CACHEINHIBIT) 425 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 426 #endif 427 428 /* 429 * BAT4 32M Cache-inhibited, guarded 430 * 0xe200_0000 16M PCI-Express 1 I/O 431 * 0xe300_0000 16M PCI-Express 2 I/0 432 * Note that this is at 0xe0000000 433 */ 434 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 435 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 438 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 439 440 /* 441 * BAT5 128K Cacheable, non-guarded 442 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 443 */ 444 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 445 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 446 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 447 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 448 449 /* 450 * BAT6 32M Cache-inhibited, guarded 451 * 0xfe00_0000 32M FLASH 452 */ 453 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 454 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 455 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 456 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 457 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 458 459 /* Map the last 1M of flash where we're running from reset */ 460 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 461 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 462 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 463 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 464 | BATL_MEMCOHERENCE) 465 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 466 467 #define CONFIG_SYS_DBAT7L 0x00000000 468 #define CONFIG_SYS_DBAT7U 0x00000000 469 #define CONFIG_SYS_IBAT7L 0x00000000 470 #define CONFIG_SYS_IBAT7U 0x00000000 471 472 /* 473 * Environment 474 */ 475 #define CONFIG_ENV_IS_IN_FLASH 1 476 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 477 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 478 #define CONFIG_ENV_SIZE 0x2000 479 480 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 481 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 482 483 #include <config_cmd_default.h> 484 #define CONFIG_CMD_PING 485 #define CONFIG_CMD_I2C 486 #define CONFIG_CMD_REGINFO 487 488 #if defined(CONFIG_PCI) 489 #define CONFIG_CMD_PCI 490 #endif 491 492 #undef CONFIG_WATCHDOG /* watchdog disabled */ 493 494 /* 495 * Miscellaneous configurable options 496 */ 497 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 498 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 499 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 500 501 #if defined(CONFIG_CMD_KGDB) 502 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 503 #else 504 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 505 #endif 506 507 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 508 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 509 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 510 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 511 512 /* 513 * For booting Linux, the board info and command line data 514 * have to be in the first 8 MB of memory, since this is 515 * the maximum mapped by the Linux kernel during initialization. 516 */ 517 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 518 519 /* Cache Configuration */ 520 #define CONFIG_SYS_DCACHE_SIZE 32768 521 #define CONFIG_SYS_CACHELINE_SIZE 32 522 #if defined(CONFIG_CMD_KGDB) 523 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 524 #endif 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 528 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 529 #endif 530 531 /* 532 * Environment Configuration 533 */ 534 535 /* The mac addresses for all ethernet interface */ 536 #if defined(CONFIG_TSEC_ENET) 537 #define CONFIG_ETHADDR 02:E0:0C:00:00:01 538 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 539 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 540 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 541 #endif 542 543 #define CONFIG_HAS_ETH0 1 544 #define CONFIG_HAS_ETH1 1 545 #define CONFIG_HAS_ETH2 1 546 #define CONFIG_HAS_ETH3 1 547 548 #define CONFIG_IPADDR 192.168.0.50 549 550 #define CONFIG_HOSTNAME sbc8641d 551 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 552 #define CONFIG_BOOTFILE "uImage" 553 554 #define CONFIG_SERVERIP 192.168.0.2 555 #define CONFIG_GATEWAYIP 192.168.0.1 556 #define CONFIG_NETMASK 255.255.255.0 557 558 /* default location for tftp and bootm */ 559 #define CONFIG_LOADADDR 1000000 560 561 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 562 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 563 564 #define CONFIG_BAUDRATE 115200 565 566 #define CONFIG_EXTRA_ENV_SETTINGS \ 567 "netdev=eth0\0" \ 568 "consoledev=ttyS0\0" \ 569 "ramdiskaddr=2000000\0" \ 570 "ramdiskfile=uRamdisk\0" \ 571 "dtbaddr=400000\0" \ 572 "dtbfile=sbc8641d.dtb\0" \ 573 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 574 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 575 "maxcpus=1" 576 577 #define CONFIG_NFSBOOTCOMMAND \ 578 "setenv bootargs root=/dev/nfs rw " \ 579 "nfsroot=$serverip:$rootpath " \ 580 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $loadaddr $bootfile;" \ 583 "tftp $dtbaddr $dtbfile;" \ 584 "bootm $loadaddr - $dtbaddr" 585 586 #define CONFIG_RAMBOOTCOMMAND \ 587 "setenv bootargs root=/dev/ram rw " \ 588 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 589 "console=$consoledev,$baudrate $othbootargs;" \ 590 "tftp $ramdiskaddr $ramdiskfile;" \ 591 "tftp $loadaddr $bootfile;" \ 592 "tftp $dtbaddr $dtbfile;" \ 593 "bootm $loadaddr $ramdiskaddr $dtbaddr" 594 595 #define CONFIG_FLASHBOOTCOMMAND \ 596 "setenv bootargs root=/dev/ram rw " \ 597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "bootm ffd00000 ffb00000 ffa00000" 600 601 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 602 603 #endif /* __CONFIG_H */ 604